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1995 microchip technology inc. ds30015m-page 1 devices included in this data sheet pic16c54 pic16cr54 h pic16c55 pic16c56 pic16c57 high-performance risc cpu features only 33 single word instructions to learn all instructions are single cycle (200 ns) except for program branches which are two-cycle operating speed: dc - 20 mhz clock input dc - 200 ns instruction cycle 12-bit wide instructions 8-bit wide data path seven or eight special function hardware registers two-level deep hardware stack direct, indirect and relative addressing modes for data and instructions peripheral features 8-bit real time clock/counter (timer0) with 8-bit programmable prescaler power-on reset (por) device reset timer (drt) watchdog timer (wdt) with its own on-chip rc oscillator for reliable operation programmable code-protection power saving sleep mode selectable oscillator options: - rc: low-cost rc oscillator - xt: standard crystal/resonator - hs: high-speed crystal/resonator - lp: power saving, low frequency crystal device pins i/o eprom/ rom ram pic16c54 18 12 512 25 pic16cr54 h 18 12 512 25 pic16c55 28 20 512 24 pic16c56 18 12 1k 25 pic16c57 28 20 2k 72 cmos technology low-power, high-speed cmos eprom/rom technology fully static design wide-operating voltage range: - eprom commercial/industrial 2.5v to 6.25v - rom commercial/industrial 2.0v to 6.25v - eprom/rom automotive 2.5v to 6.0v low-power consumption - < 2 ma typical @ 5.0v, 4 mhz - 15 m a typical @ 3.0v, 32 khz - < 3 m a typical standby current (with wdt disabled) @ 3.0v, 0 c to 70 c eprom/rom-based 8-bit cmos microcontroller series pic16c5x pin diagrams pdip, soic, windowed cerdip 18 17 16 15 14 13 12 11 10 ? 2 3 4 5 6 7 8 9 ra2 ra3 t0cki mclr /v pp v ss rb0 rb1 rb2 rb3 ra1 ra0 osc1/clkin osc2/clkout v dd rb7 rb6 rb5 rb4 28 27 26 25 24 23 22 21 20 19 18 17 16 15 ? 2 3 4 5 6 7 8 9 10 11 12 13 14 mclr /v pp osc1/clkin osc2/clkout rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 rb7 rb6 rb5 pdip, soic, windowed cerdip t0cki v dd n/c v ss n/c ra0 ra1 ra2 ra3 rb0 rb1 rb2 rb3 rb4 pic16c57 pic16c54 pic16c56 pic16c55 pic16cr54 h the pic16cr54 is not recommended for new designs. the pic16cr54a is recommended, as found in the enhanced pic16c5x data sheet. this document was created with framemake r404
pic16c5x ds30015m-page 2 1995 microchip technology inc. pin diagrams (con?) table of contents 1.0 general description .............................................................................................................................................3 2.0 pic16c5x device varieties.................................................................................................................................5 3.0 architectural overview.........................................................................................................................................7 4.0 memory organization ........................................................................................................................................13 5.0 i/o ports.............................................................................................................................................................21 6.0 timer0 module and tmr0 register...................................................................................................................23 7.0 special features of the cpu .............................................................................................................................27 8.0 instruction set summary ...................................................................................................................................39 9.0 development support ........................................................................................................................................51 10.0 electrical characteristics - pic16c54/55/56/57.................................................................................................57 11.0 dc and ac characteristics - pic16c54/55/56/57 .............................................................................................71 12.0 electrical characteristics - pic16cr54 .............................................................................................................79 13.0 dc and ac characteristics - pic16cr54 .........................................................................................................91 14.0 packaging information .....................................................................................................................................101 appendix a: compatibility................................................................................................................................115 appendix b: what? new .................................................................................................................................115 appendix c: what? changed..........................................................................................................................116 appendix d: pic16/17 microcontrollers...........................................................................................................117 index ................................................................................................................................................................125 list of examples ..............................................................................................................................................126 list of figures ..................................................................................................................................................126 list of tables ...................................................................................................................................................127 connecting to microchip bbs ..........................................................................................................................129 access to the internet ......................................................................................................................................129 reader response............................................................................................................................................130 pic16c54/55/56/57 product identification system..........................................................................................131 pic16cr54 product identification system ......................................................................................................131 ra1 ra0 osc1/clkin osc2/clkout v dd v dd rb7 rb6 rb5 rb4 ra2 ra3 t0cki mclr /v pp v ss v ss rb0 rb1 rb2 rb3 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 pic16c54 pic16cr54 pic16c56 ssop mclr /v pp osc1/clkin osc2/clkout rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 rb7 rb6 rb5 t0cki v dd v ss ra0 ra1 ra2 ra3 rb0 rb1 rb2 rb3 rb4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 pic16c57 ssop pic16c55 v dd v ss to our valued customers we constantly strive to improve the quality of all our products and documentation. we have spent an exceptional amount of time to ensure that these documents are correct. however, we realize that we may have missed a few things. if you ?d any information that is missing or appears in error, please use the reader response form in the back of this data sheet to inform us. we appreciate your assistance in making this a better document. to assist you in the use of this document, appendix b contains a list of new information in this data sheet, while appendix c contains information that has changed
1995 microchip technology inc. ds30015m-page 3 pic16c5x 1.0 general description the pic16c5x from microchip technology is a family of low-cost, high performance, 8-bit, fully static, eprom/rom-based cmos microcontrollers. this family is pin and software compatible with the enhanced pic16c5x family of devices. it employs a risc architecture with only 33 single word/single cycle instructions. all instructions are single cycle (200 ns) except for program branches which take two cycles. the pic16c5x delivers performance an order of magnitude higher than its competitors in the same price category. the 12-bit wide instructions are highly symmetrical resulting in 2:1 code compression over other 8-bit microcontrollers in its class. the easy to use and easy to remember instruction set reduces development time signi?antly. the pic16c5x products are equipped with special features that reduce system cost and power requirements. the power-on reset (por) and device reset timer (drt) eliminate the need for external reset circuitry. there are four oscillator con?urations to choose from, including the power-saving lp (low power) oscillator and cost-saving rc oscillator. power saving sleep mode, watchdog timer and code protection features improve system cost, power and reliability. the uv erasable cerdip packaged versions are ideal for code development, while the cost effective one time programmable (otp) versions are suitable for production in any volume. the customer can take full advantage of microchips price leadership in otp microcontrollers while bene?ing from the otps ?xibility. the pic16c5x products are supported by a full-featured macro assembler, a software simulator, an in-circuit emulator, a ? compiler, fuzzy logic support tools, a low-cost development programmer, and a full featured programmer. all the tools are supported on ibm pc-at and compatible machines. 1.1 applications the pic16c5x series ?s perfectly in applications ranging from high-speed automotive and appliance motor control to low-power remote transmitters/receivers, pointing devices and telecom processors. the eprom technology makes customizing application programs (transmitter codes, motor speeds, receiver frequencies, etc.) extremely fast and convenient. the small footprint packages, for through- hole or surface mounting, make this microcontroller series perfect for applications with space limitations. low-cost, low-power, high performance, ease of use and i/o ?xibility make the pic16c5x series very versatile even in areas where no microcontroller use has been considered before (e.g., timer functions, replacement of ?lue?logic in larger systems, coprocessor applications). this document was created with framemake r404
pic16c5x ds30015m-page 4 1995 microchip technology inc. table 1-1: pic16c5x family of devices pic16c54 20 512 25 tmr0 12 2.5-6.25 33 18-pin dip, soic; 20-pin ssop pic16c54a 20 512 25 tmr0 12 2.5-6.25 33 18-pin dip, soic; 20-pin ssop pic16cr54 (2) 20 512 25 tmr0 12 2.0-6.25 33 18-pin dip, soic; 20-pin ssop pic16cr54a 20 512 25 tmr0 12 2.0-6.25 33 18-pin dip, soic; 20-pin ssop pic16cr54b (1) 20 512 25 tmr0 12 2.5-6.25 33 18-pin dip, soic; 20-pin ssop pic16c55 20 512 24 tmr0 20 2.5-6.25 33 28-pin dip, soic, ssop pic16c56 20 1k 25 tmr0 12 2.5-6.25 33 18-pin dip, soic; 20-pin ssop pic16cr56 (1) 20 1k 25 tmr0 12 2.5-6.25 33 18-pin dip, soic; 20-pin ssop pic16c57 20 2k 72 tmr0 20 2.5-6.25 33 28-pin dip, soic, ssop pic16cr57a 20 2k 72 tmr0 20 2.5-6.25 33 28-pin dip, soic, ssop pic16cr57b (1) 20 2k 72 tmr0 20 2.5-6.25 33 28-pin dip, soic, ssop pic16c58a 20 2k 73 tmr0 12 2.5-6.25 33 18-pin dip, soic; 20-pin ssop pic16cr58a 20 2k 73 tmr0 12 2.5-6.25 33 18-pin dip, soic; 20-pin ssop pic16cr58b (1) 20 2k 73 tmr0 12 2.5-6.25 33 18-pin dip, soic; 20-pin ssop legend: grayed boxes: devices not covered in this data sheet all pic16/17 family devices have power-on reset, selectable watchdog timer, selectable code protect and high i/o current capability. note 1: please contact your local sales of?e for availability of these devices. 2: not recommended for new designs. maximum frequency of operation (mhz) eprom rom ram data memory (bytes) timer module(s) i/o pins voltage range (volts) number of instructions packages program memory clock memory peripherals features (words)
1995 microchip technology inc. ds30015m-page 5 pic16c5x 2.0 pic16c5x device varieties a variety of frequency ranges and packaging options are available. depending on application and production requirements, the proper device option can be selected using the information in this section. when placing orders, please use the pic16c5x product identi?ation system at the back of this data sheet to specify the correct part number. for the pic16c5x family of devices, there are two device types, as indicated in the device number: 1. c , as in pic16c54. these devices have eprom program memory and operate over the standard voltage range. 2. cr , as in pic16cr54. these devices have rom program memory and operate over the standard voltage range. 2.1 uv erasab le de vices the uv erasable versions, offered in cerdip packages, are optimal for prototype development and pilot programs. uv erasable devices can be programmed for any of the four oscillator con?urations. microchip's picstart and pro mate programmers both support programming of the pic16c5x. third party programmers also are available; refer to the third party guide for a list of sources. 2.2 one-time-pr ogrammab le (o tp) de vices the availability of otp devices is especially useful for customers expecting frequent code changes and updates. the otp devices, packaged in plastic packages, permit the user to program them once. in addition to the program memory, the con?uration bits must be programmed. 2.3 quic k-t urnar ound-pr oduction (qtp) de vices microchip offers a qtp programming service for factory production orders. this service is made available for users who choose not to program a medium to high quantity of units and whose code patterns have stabilized. the devices are identical to the otp devices but with all eprom locations and con?uration bit options already programmed by the factory. certain code and prototype veri?ation procedures apply before production shipments are available. please contact your microchip technology sales of?e for more details. 2.4 serializ ed quic k-t urnar ound-pr oduction (sqtp) de vices microchip offers the unique programming service where a few user-de?ed locations in each device are programmed with different serial numbers. the serial numbers may be random, pseudo-random or sequential. serial programming allows each device to have a unique number which can serve as an entry code, password or id number. 2.5 read onl y memor y (r om) de vices microchip offers masked rom versions of several of the highest volume parts, giving the customer a low cost option for high volume, mature products. this document was created with framemake r404
pic16c5x ds30015m-page 6 1995 microchip technology inc. notes:
1995 microchip technology inc. ds30015m-page 7 pic16c5x 3.0 architectural overview the high performance of the pic16c5x family can be attributed to a number of architectural features commonly found in risc microprocessors. to begin with, the pic16c5x uses a harvard architecture in which program and data are accessed on separate buses. this improves bandwidth over traditional von neumann architecture where program and data are fetched on the same bus. separating program and data memory further allows instructions to be sized differently than the 8-bit wide data word. instruction opcodes are 12-bits wide making it possible to have all single word instructions. a 12-bit wide program memory access bus fetches a 12-bit instruction in a single cycle. a two-stage pipeline overlaps fetch and execution of instructions. consequently, all instructions (33) execute in a single cycle (200 ns @ 20 mhz) except for program branches. the pic16c54/cr54/c55 address 512 x 12 program memory, the pic16c56 addresses 1k x 12, and the pic16c57 addresses 2k x 12 of program memory. all program memory is internal. the pic16c5x can directly or indirectly address its register ?es and data memory. all special function registers including the program counter are mapped in the data memory. the pic16c5x has a highly orthogonal (symmetrical) instruction set that makes it possible to carry out any operation on any register using any addressing mode. this symmetrical nature and lack of ?pecial optimal situations make programming with the pic16c5x simple yet ef?ient. in addition, the learning curve is reduced signi?antly. the pic16c5x device contains an 8-bit alu and working register. the alu is a general purpose arithmetic unit. it performs arithmetic and boolean functions between data in the working register and any register ?e. the alu is 8-bits wide and capable of addition, subtraction, shift and logical operations. unless otherwise mentioned, arithmetic operations are two's complement in nature. in two-operand instructions, typically one operand is the w (working) register. the other operand is a ?e register or an immediate constant. in single operand instructions, the operand is either the w register or a ?e register. the w register is an 8-bit working register used for alu operations. it is not an addressable register. depending on the instruction executed, the alu may affect the values of the carry (c), digit carry (dc), and zero (z) bits in the status register. the c and dc bits operate as a borrow and digit borrow out bit, respectively, in subtraction. see the subwf and addwf instructions for examples. a simpli?d block diagram is shown in figure 3-1, with the corresponding device pins described in table 3-1 and table 3-2. this document was created with framemake r404
pic16c5x ds30015m-page 8 1995 microchip technology inc. figure 3-1: pic16c5x series block diagram wdt time out 8 stack 1 stack 2 eprom/rom 512 x 12 to 2048 x 12 instruction register instruction decoder watchdog timer configuration word oscillator/ timing & control general purpose register file (sram) 24, 25 or 72 bytes wdt/tmr0 prescaler option reg. ?ption ?leep ?ode protect ?sc select direct address tmr0 from w from w ?ris 5 ?ris 6 ?ris 7 fsr trisa porta trisb portc trisc portb from w t0cki pin 9-11 9-11 12 12 8 w 4 4 4 data bus 8 8 8 8 8 8 8 alu status from w clkout 8 9 6 5 5-7 osc1 osc2 mclr literals pc ?isable 2 ra3:ra0 rb7:rb0 rc7:rc0 (28 pin devices only) direct ram address
1995 microchip technology inc. ds30015m-page 9 pic16c5x table 3-1: pic16c54/cr54/c56 pinout description name dip, soic no. ssop no. i/o/p type input levels description ra0 ra1 ra2 ra3 17 18 1 2 19 20 1 2 i/o i/o i/o i/o ttl ttl ttl ttl bi-directional i/o port rb0 rb1 rb2 rb3 rb4 rb5 rb6 rb7 6 7 8 9 10 11 12 13 7 8 9 10 11 12 13 14 i/o i/o i/o i/o i/o i/o i/o i/o ttl ttl ttl ttl ttl ttl ttl ttl bi-directional i/o port t0cki 3 3 i st clock input to timer0. must be tied to v ss or v dd, if not in use, to reduce current consumption. mclr/ v pp 4 4 i st master clear (reset) input/programming voltage input. this pin is an active low reset to the device. voltage on mclr / v pp must not exceed v dd to avoid unintended entering of programming mode. osc1/clkin 16 18 i st oscillator crystal input/external clock source input. osc2/clkout 15 17 o oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. in rc mode, osc2 pin outputs clkout which has 1/4 the frequency of osc1, and denotes the instruction cycle rate. v dd 14 15,16 p positive supply for logic and i/o pins. v ss 5 5,6 p ground reference for logic and i/o pins. legend: i = input, o = output, i/o = input/output, p = power, ?= not used, ttl = ttl input, st = schmitt trigger input
pic16c5x ds30015m-page 10 1995 microchip technology inc. table 3-2: pic16c55/c57 pinout description name dip, soic no. ssop no. i/o/p type input levels description ra0 ra1 ra2 ra3 6 7 8 9 5 6 7 8 i/o i/o i/o i/o ttl ttl ttl ttl bi-directional i/o port rb0 rb1 rb2 rb3 rb4 rb5 rb6 rb7 10 11 12 13 14 15 16 17 9 10 11 12 13 15 16 17 i/o i/o i/o i/o i/o i/o i/o i/o ttl ttl ttl ttl ttl ttl ttl ttl bi-directional i/o port rc0 rc1 rc2 rc3 rc4 rc5 rc6 rc7 18 19 20 21 22 23 24 25 18 19 20 21 22 23 24 25 i/o i/o i/o i/o i/o i/o i/o i/o ttl ttl ttl ttl ttl ttl ttl ttl bi-directional i/o port t0cki 1 2 i st clock input to timer0. must be tied to v ss or v dd, if not in use, to reduce current consumption. mclr/ v pp 28 28 i st master clear (reset) input/programming voltage input. this pin is an active low reset to the device. voltage on mclr/ v pp must not exceed v dd to avoid unintended entering of programming mode. osc1/clkin 27 27 i st oscillator crystal input/external clock source input. osc2/clkout 26 26 o oscillator crystal output. connects to crystal or resonator in crystal oscillator mode. in rc mode, osc2 pin outputs clkout which has 1/4 the frequency of osc1, and denotes the instruction cycle rate. v dd 2 3,4 p positive supply for logic and i/o pins. v ss 4 1,14 p ground reference for logic and i/o pins. n/c 3,5 unused, do not connect legend: i = input, o = output, i/o = input/output, p = power, ?= not used, ttl = ttl input, st = schmitt trigger input
1995 microchip technology inc. ds30015m-page 11 pic16c5x 3.1 cloc king sc heme/ instruction cyc le the clock input (osc1/clkin pin) is internally divided by four to generate four non-overlapping quadrature clocks namely q1, q2, q3 and q4. internally, the program counter (pc) is incremented every q1, and the instruction is fetched from program memory and latched into the instruction register in q4. it is decoded and executed during the following q1 through q4. the clocks and instruction execution ?w is shown in figure 3-2 and example 3-1. 3.2 instruction flo w/pipelining an instruction cycle consists of four q cycles (q1, q2, q3 and q4). the instruction fetch and execute are pipelined such that fetch takes one instruction cycle while decode and execute takes another instruction cycle. however, due to the pipelining, each instruction effectively executes in one cycle. if an instruction causes the program counter to change (e.g., goto ) then two cycles are required to complete the instruction (example 3-1). a fetch cycle begins with the program counter (pc) incrementing in q1. in the execution cycle, the fetched instruction is latched into the instruction register (ir) in cycle q1. this instruction is then decoded and executed during the q2, q3, and q4 cycles. data memory is read during q2 (operand read) and written during q4 (destination write). figure 3-2: clock/instruction cycle example 3-1: instruction pipeline flow q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 q1 q2 q3 q4 pc osc2/clkout (rc mode) pc pc+1 pc+2 fetch inst (pc) execute inst (pc-1) fetch inst (pc+1) execute inst (pc) fetch inst (pc+2) execute inst (pc+1) internal phase clock all instructions are single cycle, except for any program branches. these take two cycles since the fetch instruction is ushed?from the pipeline while the new instruction is being fetched and then executed. 1. movlw 55h fetch 1 execute 1 2. movwf portb fetch 2 execute 2 3. call sub_1 fetch 3 execute 3 4. bsf porta, bit3 fetch 4 flush fetch sub_1 execute sub_1
pic16c5x ds30015m-page 12 1995 microchip technology inc. notes:
1995 microchip technology inc. ds30015m-page 13 pic16c5x 4.0 memory organization 4.1 pr ogram memor y or ganization the pic16c54, pic16cr54 and pic16c55 have a 9-bit program counter (pc) capable of addressing a 512 x 12 program memory space (figure 4-1). the pic16c56 has a 10-bit program counter capable of addressing a 1k x 12 program memory space (figure 4-2). the pic16c57 has an 11-bit program counter capable of addressing a 2k x 12 program memory space (figure 4-3). accessing a location above the physically implemented address will cause a wraparound. the reset vector for the pic16c54/cr54/c55 is at 1ffh, at 3ffh for the pic16c56, and at 7ffh for the pic16c57. figure 4-1: pic16c54/cr54/c55 program memory map and stack figure 4-2: pic16c56 program memory map and stack pc<8:0> stack level 1 stack level 2 user memory space call, retlw 9 000h 1ffh reset vector 0ffh 100h on-chip program memory pc<9:0> stack level 1 stack level 2 user memory space 10 000h 1ffh reset vector 0ffh 100h on-chip program memory (page 0) on-chip program memory (page 1) 200h 3ffh 2ffh 300h call, retlw figure 4-3: pic16c57 program memory map and stack 4.2 d ata memor y or ganizatio n data memory is composed of registers, or bytes of ram. therefore, data memory for a device is speci?d by its register ?e. the register ?e is divided into two functional groups: special function registers and general purpose registers. the special function registers include the tmr0 register, the program counter (pc), the status register, the i/o registers (ports), and the file select register (fsr). in addition, special purpose registers are used to control the i/o port con?uration and prescaler options. the general purpose registers are used for data and control information under command of the instructions. for the pic16c54, pic16cr54 and pic16c56, the register ?e is composed of seven special function registers and 25 general purpose registers (figure 4-4). for the pic16c55, the register ?e is composed of eight special function registers and 24 general purpose registers (figure 4-5). for the pic16c57, up to 48 additional general purpose registers may be addressed using a banking scheme (figure 4-6). 4.2.1 general purpose register file the register ?e is accessed either directly or indirectly through the ?e select register fsr (section 4.7). pc<10:0> stack level 1 stack level 2 user memory space 11 000h 1ffh reset vector 0ffh 100h on-chip program memory (page 0) on-chip program memory (page 1) on-chip program memory (page 2) on-chip program memory (page 3) 200h 3ffh 2ffh 300h 400h 5ffh 4ffh 500h 600h 7ffh 6ffh 700h call, retlw this document was created with framemake r404
pic16c5x ds30015m-page 14 1995 microchip technology inc. figure 4-4: pic16c54/cr54/c56 register file map file address 00h 01h 02h 03h 04h 05h 06h 07h 1fh indf (1) tmr0 pcl status fsr porta portb general purpose registers note 1: not a physical register. see section 4.7 0fh 10h figure 4-5: pic16c55 register file map file address 00h 01h 02h 03h 04h 05h 06h 07h 1fh indf (1) tmr0 pcl status fsr porta portb general purpose registers 0fh 10h portc 08h note 1: not a physical register. see section 4.7 figure 4-6: pic16c57 register file map file address 00h 01h 02h 03h 04h 05h 06h 07h 1fh indf (1) tmr0 pcl status fsr porta portb 0fh 10h bank 0 bank 1 bank 2 bank 3 3fh 30h 20h 2fh 5fh 50h 40h 4fh 7fh 70h 60h 6fh general purpose register general purpose registers general purpose registers general purpose registers general purpose registers portc 08h addresses map back to addresses in bank 0. note 1: not a physical register. see section 4.7 fsr<6:5> 00 01 10 11
1995 microchip technology inc. ds30015m-page 15 pic16c5x 4.2.2 special function registers the special function registers are registers used by the cpu and peripheral functions to control the operation of the device (table 4-1). the special registers can be classi?d into two sets. the special function registers associated with the ?ore?functions are described in this section. those related to the operation of the peripheral features are described in the section for each peripheral feature. table 4-1: special function register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset value on mclr and wdt reset n/a tris i/o control registers (trisa, trisb, trisc) 1111 1111 1111 1111 n/a option contains control bits to con?ure timer0 and timer0/wdt prescaler --11 1111 --11 1111 00h indf uses contents of fsr to address data memory (not a physical register) xxxx xxxx uuuu uuuu 01h tmr0 8-bit real-time clock/counter xxxx xxxx uuuu uuuu 02h (1) pcl low order 8 bits of pc 1111 1111 1111 1111 03h status pa2 pa1 pa0 t o pd zdcc 0001 1xxx 000q quuu 04h fsr indirect data memory address pointer 1xxx xxxx 1uuu uuuu 05h porta ra3 ra2 ra1 ra0 ---- xxxx ---- uuuu 06h portb rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 xxxx xxxx uuuu uuuu 07h (2) portc rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 xxxx xxxx uuuu uuuu legend: shaded boxes = unimplemented or unused, ?= unimplemented, read as '0' (if applicable) x = unknown, u = unchanged, q = see the tables in section 7.7 for possible values. note 1: the upper byte of the program counter is not directly accessible. see section 4.5 for an explanation of how to access these bits. 2: file address 07h is a general purpose register on the pic16c54/cr54/c56.
pic16c5x ds30015m-page 16 1995 microchip technology inc. 4.3 st a tus register this register contains the arithmetic status of the alu, the reset status, and the page preselect bits for program memories larger than 512 words. the status register can be the destination for any instruction, as with any other register. if the status register is the destination for an instruction that affects the z, dc or c bits, then the write to these three bits is disabled. these bits are set or cleared according to the device logic. furthermore, the t o and pd bits are not writable. therefore, the result of an instruction with the status register as destination may be different than intended. for example, clrf status will clear the upper three bits and set the z bit. this leaves the status register as 000u u1uu (where u = unchanged). it is recommended, therefore, that only bcf , bsf and movwf instructions be used to alter the status register because these instructions do not affect the z, dc or c bits from the status register. for other instructions which do affect status bits, see table 8-2, instruction set summary. figure 4-7: status register (address:03h) r/w-0 r/w-0 r/w-0 r-1 r-1 r/w-x r/w-x r/w-x pa2 pa1 pa0 t o pd z dc c r = readable bit w = writable bit - n = value at por reset bit7 6 5 4 3 2 1 bit0 bit 7: pa2 : this bit unused at this time. use of the pa2 bit as a general purpose read/write bit is not recommended, since this may affect upward compatibility with future products. bit 6-5: pa1:pa0 : program page preselect bits (pic16c56 and pic16c57 only) 00 = page 0 (000h - 1ffh) - pic16c56 and pic16c57 01 = page 1 (200h - 3ffh) - pic16c56 and pic16c57 10 = page 2 (400h - 5ffh) - pic16c57 11 = page 3 (600h - 7ffh) - pic16c57 each page is 512 bytes. using the pa1:pa0 bits as general purpose read/write bits in devices which do not use them for program page preselect is not recommended since this may affect upward compatibility with future products. bit 4: t o : time-out bit 1 = after power-up, clrwdt instruction, or sleep instruction 0 = a wdt time-out occurred bit 3: pd : power-down bit 1 = after power-up or by the clrwdt instruction 0 = by execution of the sleep instruction bit 2: z : zero bit 1 = the result of an arithmetic or logic operation is zero 0 = the result of an arithmetic or logic operation is not zero bit 1: dc : digit carry/borrow bit (for addwf and subwf instructions) addwf 1 = a carry from the 4th low order bit of the result occurred 0 = a carry from the 4th low order bit of the result did not occur subwf 1 = a borrow from the 4th low order bit of the result did not occur 0 = a borrow from the 4th low order bit of the result occurred bit 0: c : carry/borrow bit (for addwf , subwf and rrf , rlf instructions) addwf subwf rrf or rlf 1 = a carry occurred 1 = a borrow did not occur load bit with lsb or msb 0 = a carry did not occur 0 = a borrow occurred
1995 microchip technology inc. ds30015m-page 17 pic16c5x 4.4 o ption register the option register is a 6-bit wide, write-only register which contains various control bits to con?ure the timer0/wdt prescaler and timer0. by executing the option instruction, the contents of the w register will be transferred to the option register. a reset sets the option<5:0> bits. figure 4-8: option register u-0 u-0 w-1 w-1 w-1 w-1 w-1 w-1 t0cs t0se psa ps2 ps1 ps0 w = writable bit u = unimplemented bit - n = value at por reset bit7 6 5 4 3 2 1 bit0 bit 7-6: unimplemented . bit 5: t0cs : timer0 clock source select bit 1 = transition on t0cki pin 0 = internal instruction cycle clock (clkout) bit 4: t0se : timer0 source edge select bit 1 = increment on high-to-low transition on t0cki pin 0 = increment on low-to-high transition on t0cki pin bit 3: psa : prescaler assignment bit 1 = prescaler assigned to the wdt 0 = prescaler assigned to timer0 bit 2-0: ps2:ps0 : prescaler rate select bits 000 001 010 011 100 101 110 111 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 bit value timer0 rate wdt rate
pic16c5x ds30015m-page 18 1995 microchip technology inc. 4.5 p r ogram counter as a program instruction is executed, the program counter (pc) will contain the address of the next program instruction to be executed. the pc value is increased by one every instruction cycle, unless an instruction changes the pc. for a goto instruction, bits 8:0 of the pc are provided by the goto instruction word. the pc latch (pcl) is mapped to pc<7:0> (figure 4-9, figure 4-10 and figure 4-11). for the pic16c56 and pic16c57, a page number must be supplied as well. bit5 of the status register provides this to bit9 of the pc for the pic16c56 (figure 4-10). bit5 and bit6 of the status register provide page information to bit9 and bit10 of the pc for the pic16c57 (figure 4-11). for a call instruction, or any instruction where the pcl is the destination, bits 7:0 of the pc are provided by the instruction word. however, pc<8> does not come from the instruction word, but is always cleared (figure 4-9, figure 4-10 and figure 4-11). instructions where the pcl is the destination, or modify pcl instructions, include movwf pc, addwf pc, and bsf pc,5. for the pic16c56 and pic16c57, a page number again must be supplied. bit5 of the status register provides this to bit9 of the pc for the pic16c56 (figure 4-10). bit5 and bit6 of the status register provide page information to bit9 and bit10 of the pc for the pic16c57 (figure 4-11). figure 4-9: loading of pc branch instructions - pic16c54/cr54/c55 note: because pc<8> is cleared in the call instruction, or any modify pcl instruction, all subroutine calls or computed jumps are limited to the ?st 256 locations of any program memory page (512 words long). pc 87 0 pcl pc 87 0 pcl reset to '0' instruction word instruction word goto instruction call or modify pcl instruction figure 4-10: loading of pc branch instructions - pic16c56 figure 4-11: loading of pc branch instructions - pic16c57 reset to '0' pa0 status pc 87 0 pcl 9 pa0 status pc 87 0 pcl 9 instruction word instruction word 70 70 call or modify pcl instruction goto instruction pa1:pa0 2 status pc 87 0 pcl 9 10 pa1:pa0 2 status pc 87 0 pcl 9 10 instruction word reset to ? instruction word 70 70 goto instruction call or modify pcl instruction
1995 microchip technology inc. ds30015m-page 19 pic16c5x for the retlw instruction, the pc is loaded with the top of stack (tos) contents. all of the devices covered in this data sheet have only two stacks. each stack has the same bit width as the device pc. 4.5.1 paging considerations ? pic16c56/57 if the program counter is pointing to the last address of a selected memory page, when it increments it will cause the program to continue in the next higher page. however, the page preselect bits in the status register will not be updated. therefore, the next goto , call , or modify pcl instruction will return the program to the page speci?d by the page preselect bits (pa0 or pa1:pa0). for example, a nop at location 1ffh (page 0) increments the pc to 200h (page 1). a goto xxx at 200h will return the program to address xxxh on page 0 (assuming that pa1:pa0 are clear). to prevent this, the page preselect bits must be updated under program control. 4.5.2 effects of reset the program counter is set upon a reset, which means that the pc addresses the last location in the last page (i.e., the reset vector). the status register page preselect bits are cleared upon a reset, which means that page 0 is pre-selected. therefore, upon a reset, a goto instruction at the reset vector location will automatically cause the program to jump to page 0. if an inadequate reset occurs (i.e., por conditions are not met, a brown-out occurs, etc.), page preselect bits in the status register will not be cleared. therefore, it is good programming practice to include the following code before the goto instruction at the reset vector location: bsf status bsf fsr 4.6 stac k pic16c5x devices have a 9-bit, 10-bit or 11-bit wide, two-level hardware push/pop stack (figure 4-1, figure 4-2 and figure 4-3 respectively). a call instruction will push the current value of stack 1 into stack 2 and then push the current program counter value, incremented by one, into stack level 1. if more than two sequential call s are executed, only the most recent two return addresses are stored. a retlw instruction will pop the contents of stack level 1 into the program counter and then copy stack level 2 contents into level 1. if more than two sequential retlw s are executed, the stack will be filled with the address previously stored in level 2. note: the w register will be loaded with the literal value speci?d in the instruction. this is particularly useful for the implementation of data look-up tables within the program memory.
pic16c5x ds30015m-page 20 1995 microchip technology inc. 4.7 indirect data ad dressing; indf and fsr register s the indf register is not a physical register. addressing indf actually addresses the register whose address is contained in the fsr register (fsr is a pointer ). this is indirect addressing. example 4-1: indirect addressing register ?e 05 contains the value 10h register ?e 06 contains the value 0ah load the value 05 into the fsr register a read of the indf register will return the value of 10h increment the value of the fsr register by one (fsr = 06) a read of the indr register now will return the value of 0ah. reading indf itself indirectly (fsr = 0) will produce 00h. writing to the indf register indirectly results in a no-operation (although status bits may be affected). a simple program to clear ram locations 10h-1fh using indirect addressing is shown in example 4-2. example 4-2: how to clear ram using indirect addressing movlw 0x10 ;initialize pointer movwf fsr ; to ram next clrf indf ;clear indf register incf fsr,f ;inc pointer btfsc fsr,4 ;all done? goto next ;no, clear next continue : ;yes, continue the fsr is either a 5-bit (pic16c54/cr54/c55/c56) or 7-bit (pic16c57) wide register. it is used in conjunction with the indf register to indirectly address the data memory area. the last two bits, fsr<6:5>, are also used on the pic16c57 for direct addressing (figure 4-12). the fsr<4:0> bits are used to select data memory addresses 00h to 1fh. pic16c54/cr54/c55/c56: do not use banking. fsr<6:5> are unimplemented and read as '1's. pic16c57: fsr<6:5> are the bank select bits and are used to select the bank to be addressed ( 00 = bank 0, 01 = bank 1, 10 = bank 2, 11 = bank 3). figure 4-12: direct/indirect addressing note 1: for register map detail see section 4.2. bank location select location select bank select indirect addressing direct addressing data memory (1) 0fh 10h bank 0 bank 1 bank 2 bank 3 0 4 5 6 (fsr) 10 00 01 11 00h 1fh 3fh 5fh 7fh (opcode) 0 4 5 6 (fsr) addresses map back to addresses in bank 0.
1995 microchip technology inc. ds30015m-page 21 pic16c5x 5.0 i/o ports as with any other register, the i/o registers can be written and read under program control. however, read instructions (e.g., movf portb,w ) always read the i/o pins independent of the pins input/output modes. on reset, all i/o ports are de?ed as input (inputs are at hi-impedance) since the i/o control registers (trisa, trisb, trisc) are all set. 5.1 por t a porta is a 4-bit i/o register. only the low order 4 bits are used (ra3:ra0). bits 7-4 are unimplemented and read as '0's. 5.2 por tb portb is an 8-bit i/o register (portb<7:0>). 5.3 por tc pic16c55/c57: 8-bit i/o register. pic16c54/cr54/c56: general purpose register. 5.4 tris register s the output driver control registers are loaded with the contents of the w register by executing the tris f instruction. a '1' from a tris register bit puts the corresponding output driver in a hi-impedance mode. a '0' puts the contents of the output data latch on the selected pins, enabling the output buffer. the tris registers are ?rite-only?and are set (output drivers disabled) upon reset. note: a read of the ports reads the pins, not the output data latches. that is, if an output driver on a pin is enabled and driven high, but the external system is holding it low, a read of the port will indicate that the pin is low. 5.5 i/o interfacing the equivalent circuit for an i/o port pin is shown in figure 5-1. all ports may be used for both input and output operations. for input operations these ports are non-latching. any input must be present until read by an input instruction (e.g., movf portb, w ). the outputs are latched and remain unchanged until the output latch is rewritten. to use a port pin as output, the corresponding direction control bit (in trisa, trisb, trisc) must be cleared (= 0). for use as an input, the corresponding tris bit must be set. any i/o pin can be programmed individually as input or output. figure 5-1: equivalent circuit for a single i/o pin note 1: i/o pins have protection diodes to v dd and v ss . data bus q d q ck q d q ck p n wr port tris ? data tris rd port v ss v dd i/o pin (1) w reg latch latch reset table 5-1: summary of port registers address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset value on mclr and wdt reset n/a tris i/o control registers (trisa, trisb, trisc) 1111 1111 1111 1111 05h porta ra3 ra2 ra1 ra0 ---- xxxx ---- uuuu 06h portb rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 xxxx xxxx uuuu uuuu 07h (1) portc rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 xxxx xxxx uuuu uuuu legend: shaded boxes = unimplemented, read as ?? = unimplemented, read as '0', x = unknown, u = unchanged note 1: file address 07h is a general purpose register on the pic16c54/cr54/c56. this document was created with framemake r404
pic16c5x ds30015m-page 22 1995 microchip technology inc. 5.6 i/o pr ogramming considerations 5.6.1 bi-directional i/o ports some instructions operate internally as read followed by write operations. the bcf and bsf instructions, for example, read the entire port into the cpu, execute the bit operation and re-write the result. caution must be used when these instructions are applied to a port where one or more pins are used as input/outputs. for example, a bsf operation on bit5 of portb will cause all eight bits of portb to be read into the cpu, bit5 to be set and the portb value to be written to the output latches. if another bit of portb is used as a bi-directional i/o pin (say bit0) and it is de?ed as an input at this time, the input signal present on the pin itself would be read into the cpu and rewritten to the data latch of this particular pin, overwriting the previous content. as long as the pin stays in the input mode, no problem occurs. however, if bit0 is switched into output mode later on, the content of the data latch may now be unknown. example 5-1 shows the effect of two sequential read-modify-write instructions (e.g., bcf, bsf , etc.) on an i/o port. a pin actively outputting a high or a low should not be driven from external devices at the same time in order to change the level on this pin (?ired-or? ?ired-and?. the resulting high output currents may damage the chip. example 5-1: read-modify-write instructions on an i/o port ;initial port settings ; portb<7:4> inputs ; portb<3:0> outputs ;portb<7:6> have external pull-ups and are ;not connected to other circuitry ; ; port latch port pins ; ---------- ---------- bcf portb, 7 ;01pp pppp 11pp pppp bcf portb, 6 ;10pp pppp 11pp pppp movlw 03fh ; tris portb ;10pp pppp 10pp pppp ; ;note that the user may have expected the pin ;values to be 00pp pppp. the 2nd bcf caused ;rb7 to be latched as the pin value (high). 5.6.2 successive operations on i/o ports the actual write to an i/o port happens at the end of an instruction cycle, whereas for reading, the data must be valid at the beginning of the instruction cycle (figure 5-2). therefore, care must be exercised if a write followed by a read operation is carried out on the same i/o port. the sequence of instructions should allow the pin voltage to stabilize (load dependent) before the next instruction, which causes that ?e to be read into the cpu, is executed. otherwise, the previous state of that pin may be read into the cpu rather than the new state. when in doubt, it is better to separate these instructions with a nop or another instruction not accessing this i/o port. figure 5-2: successive i/o operation pc pc + 1 pc + 2 pc + 3 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 instruction fetched rb7:rb0 movwf portb nop port pin sampled here nop movf portb,w instruction executed movwf portb (write to portb) nop movf portb,w this example shows a write to portb followed by a read from portb. data setup time = (0.25 t cy ?t pd ) where: t cy = instruction cycle. t pd = propagation delay therefore, at higher clock frequencies, a write followed by a read may be problematic. (read portb) port pin written here
1995 microchip technology inc. ds30015m-page 23 pic16c5x 6.0 timer0 module and tmr0 register the timer0 module has the following features: 8-bit timer/counter register, tmr0 - readable and writable 8-bit software programmable prescaler internal or external clock select - edge select for external clock figure 6-1 is a simpli?d block diagram of the timer0 module, while figure 6-2 shows the electrical structure of the timer0 input. timer mode is selected by clearing the t0cs bit (option<5>). in timer mode, the timer0 module will increment every instruction cycle (without prescaler). if tmr0 register is written, the increment is inhibited for the following two cycles (figure 6-3 and figure 6-4). the user can work around this by writing an adjusted value to the tmr0 register. counter mode is selected by setting the t0cs bit (option<5>). in this mode, timer0 will increment either on every rising or falling edge of pin t0cki. the incrementing edge is determined by the source edge select bit t0se (option<4>). clearing the t0se bit selects the rising edge. restrictions on the external clock input are discussed in detail in section 6.1. the prescaler may be used by either the timer0 module or the watchdog timer, but not both. the prescaler assignment is controlled in software by the control bit psa (option<3>). clearing the psa bit will assign the prescaler to timer0. the prescaler is not readable or writable. when the prescaler is assigned to the timer0 module, prescale values of 1:2, 1:4,..., 1:256 are selectable. section 6.2 details the operation of the prescaler. a summary of registers associated with the timer0 module is found in table 6-1. figure 6-1: timer0 block diagram figure 6-2: electrical structure of t0cki pin note 1: bits t0cs, t0se, psa, ps2, ps1 and ps0 are located in the option register. 2: the prescaler is shared with the watchdog timer (figure 6-6). t0cki t0se (1) 0 1 1 0 pin t0cs (1) f osc /4 programmable prescaler (2) sync with internal clocks tmr0 reg psout (2 cycle delay) psout data bus 8 psa (1) ps2, ps1, ps0 (1) 3 sync v ss v ss r in schmitt trigger n input buffer t0cki pin note 1: esd protection circuits (1) (1) this document was created with framemake r404
pic16c5x ds30015m-page 24 1995 microchip technology inc. figure 6-3: timer0 timing: internal clock/no prescale figure 6-4: timer0 timing: internal clock/prescale 1:2 table 6-1: registers associated with timer0 address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset value on mclr and wdt reset 01 tmr0 timer0 - 8-bit real-time clock/counter xxxx xxxx uuuu uuuu n/a option t0cs t0se psa ps2 ps1 ps0 --11 1111 --11 1111 legend: shaded cells: unimplemented bits, - = unimplemented, x = unknown, u = unchanged, pc-1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 pc (program counter) instruction fetch timer0 pc pc+1 pc+2 pc+3 pc+4 pc+5 pc+6 t0 t0+1 t0+2 nt0 nt0 nt0 nt0+1 nt0+2 movwf tmr0 movf tmr0,w movf tmr0,w movf tmr0,w movf tmr0,w movf tmr0,w write tmr0 executed read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 + 1 read tmr0 reads nt0 + 2 instruction executed pc-1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 pc (program counter) instruction fetch timer0 pc pc+1 pc+2 pc+3 pc+4 pc+5 pc+6 t0 nt0+1 movwf tmr0 movf tmr0,w movf tmr0,w movf tmr0,w movf tmr0,w movf tmr0,w write tmr0 executed read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 read tmr0 reads nt0 + 1 t0+1 nt0 instruction execute t0
1995 microchip technology inc. ds30015m-page 25 pic16c5x 6.1 using t imer0 with an external cloc k when an external clock input is used for timer0, it must meet certain requirements. the external clock requirement is due to internal phase clock (t osc ) synchronization. also, there is a delay in the actual incrementing of timer0 after synchronization. 6.1.1 external clock synchronization when no prescaler is used, the external clock input is the same as the prescaler output. the synchronization of t0cki with the internal phase clocks is accomplished by sampling the prescaler output on the q2 and q4 cycles of the internal phase clocks (figure 6-5). therefore, it is necessary for t0cki to be high for at least 2t osc (and a small rc delay of 20 ns) and low for at least 2t osc (and a small rc delay of 20 ns). refer to the electrical speci?ation of the desired device. when a prescaler is used, the external clock input is divided by the asynchronous ripple counter-type prescaler so that the prescaler output is symmetrical. for the external clock to meet the sampling requirement, the ripple counter must be taken into account. therefore, it is necessary for t0cki to have a period of at least 4t osc (and a small rc delay of 40 ns) divided by the prescaler value. the only requirement on t0cki high and low time is that they do not violate the minimum pulse width requirement of 10 ns. refer to parameters 40, 41 and 42 in the electrical speci?ation of the desired device. 6.1.2 timer0 increment delay since the prescaler output is synchronized with the internal clocks, there is a small delay from the time the external clock edge occurs to the time the timer0 module is actually incremented. figure 6-5 shows the delay from the external clock edge to the timer incrementing. figure 6-5: timer0 timing with external clock increment timer0 (q4) external clock input or q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 timer0 t0 t0 + 1 t0 + 2 small pulse misses sampling external clock/prescaler output after sampling (3) note 1: 2: 3: delay from clock input change to timer0 increment is 3tosc to 7tosc. (duration of q = tosc). therefore, the error in measuring the interval between two edges on timer0 input = 4tosc max. external clock if no prescaler selected, prescaler output otherwise. the arrows indicate the points in time where sampling occurs. prescaler output (2) (1)
pic16c5x ds30015m-page 26 1995 microchip technology inc. 6.2 prescaler an 8-bit counter is available as a prescaler for the timer0 module, or as a postscaler for the watchdog timer (wdt), respectively (section 6.1.2). for simplicity, this counter is being referred to as ?rescaler?throughout this data sheet. note that the prescaler may be used by either the timer0 module or the wdt, but not both. thus, a prescaler assignment for the timer0 module means that there is no prescaler for the wdt, and vice-versa. the psa and ps2:ps0 bits (option<3:0>) determine prescaler assignment and prescale ratio. when assigned to the timer0 module, all instructions writing to the tmr0 register (e.g., clrf 1, movwf 1, bsf 1,x, etc.) will clear the prescaler. when assigned to wdt, a clrwdt instruction will clear the prescaler along with the wdt. the prescaler is neither readable nor writable. on a reset, the prescaler contains all '0's. 6.2.1 switching prescaler assignment the prescaler assignment is fully under software control (i.e., it can be changed ?n the ??during program execution). to avoid an unintended device reset, the following instruction sequence (example 6-1) must be executed when changing the prescaler assignment from timer0 to the wdt. example 6-1: changing prescaler (timer0 wdt) clrf tmr0 ;clear tmr0 clrwdt ;clears wdt and ;prescaler movlw 'xxxx1xxx' ;select new prescale option ;value to change prescaler from the wdt to the timer0 module, use the sequence shown in example 6-2. this sequence must be used even if the wdt is disabled. a clrwdt instruction should be executed before switching the prescaler. example 6-2: changing prescaler (wdt timer0) clrwdt ;clear wdt and ;prescaler movlw 'xxxx0xxx' ;select tmr0, new ;prescale value and ;clock source option figure 6-6: block diagram of the timer0/wdt prescaler t0cki t0se pin t cy ( = fosc/4) sync 2 cycles tmr0 reg 8-bit prescaler 8 - to - 1mux m mux watchdog timer psa 0 1 0 1 wdt time-out ps2:ps0 8 note: t0cs, t0se, psa, ps2:ps0 are bits in the option register. psa wdt enable bit 0 1 0 1 data bus 8 psa t0cs m u x m u x u x
1995 microchip technology inc. ds30015m-page 27 pic16c5x 7.0 special features of the cpu what sets a microcontroller apart from other processors are special circuits to deal with the needs of real-time applications. the pic16c5x family of microcontrollers has a host of such features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection. these features are: oscillator selection reset power-on reset (por) device reset timer (drt) watchdog timer (wdt) sleep code protection id locations the pic16c5x has a watchdog timer which can be shut off only through con?uration bit wdte. it runs off of its own rc oscillator for added reliability. there is an 18 ms delay provided by the device reset timer (drt), intended to keep the chip in reset until the crystal oscillator is stable. with this timer on-chip, most applications need no external reset circuitry. the sleep mode is designed to offer a very low current power-down mode. the user can wake up from sleep through external reset or through a watchdog timer time-out. several oscillator options are also made available to allow the part to ? the application. the rc oscillator option saves system cost while the lp crystal option saves power. a set of con?uration bits are used to select various options. 7.1 c on guration bits the pic16c5x con?uration word consists of 12 bits, 4 of which are implemented. con?uration bits can be programmed to select various device con?urations. two bits are for the selection of the oscillator type, one bit is the watchdog timer enable bit and one bit is the code protection bit (figure 7-1). otp, qtp or rom devices have the oscillator con?uration programmed at the factory and these parts are tested accordingly (see "product identi?ation system" on the inside back cover). figure 7-1: configuration word for pic16c54/cr54/c55/c56/c57 cp wdte fosc1 fosc0 register: config address (1) : fffh bit11 10 987654321 bit0 bit 11-4: unimplemented: read as ?? bit 3: cp: code protection bit 1 = code protection off 0 = code protection on bit 2: wdte: watchdog timer enable bit 1 = wdt enabled 0 = wdt disabled bit 1-0: fosc1:fosc0: oscillator selection bits 11 = rc oscillator 10 = hs oscillator 01 = xt oscillator 00 = lp oscillator note 1: refer to the pic16c5x programming speci?ations (literature number ds30190) to determine how to access the con?uration word. this document was created with framemake r404
pic16c5x ds30015m-page 28 1995 microchip technology inc. preliminary table 7-1: capacitor selection for ceramic resonators - pic16c54/55/56/57 table 7-2: capacitor selection for crystal oscillator - pic16c54/55/56/57 osc type resonator freq cap. range c1 cap. range c2 xt 455 khz 2.0 mhz 4.0 mhz 68-100 pf 15-33 pf 10-22 pf 68-100 pf 15-33 pf 10-22 pf hs 8.0 mhz 16.0 mhz 10-22 pf 10 pf 10-22 pf 10 pf these values are for design guidance only. since each resonator has its own characteristics, the user should consult the resonator manufacturer for appropriate values of external components. osc type resonator freq cap.range c1 cap. range c2 lp 32 khz (1) 15 pf 15 pf xt 100 khz 200 khz 455 khz 1 mhz 2 mhz 4 mhz 15-30 pf 15-30 pf 15-30 pf 15-30 pf 15 pf 15 pf 200-300 pf 100-200 pf 15-100 pf 15-30 pf 15 pf 15 pf hs 4 mhz 8 mhz 20 mhz 15 pf 15 pf 15 pf 15 pf 15 pf 15 pf note 1: for v dd > 4.5v, c1 = c2 ? 30pf is recom- mended. these values are for design guidance only. rs may be required in hs mode as well as xt mode to avoid overdriving crystals with low drive level speci?ation. since each crystal has its own characteristics, the user should consult the crystal manufacturer for appropriate values of external components. 7.2 oscillator con gurations 7.2.1 oscillator types the pic16c5x can be operated in four different oscillator modes. the user can program two con?uration bits (fosc1:fosc0) to select one of these four modes: lp: low power crystal xt: crystal/resonator hs: high speed crystal/resonator rc: resistor/capacitor 7.2.2 crystal oscillator / ceramic resonators in xt, lp or hs modes, a crystal or ceramic resonator is connected to the osc1/clkin and osc2/clkout pins to establish oscillation (figure 7-2). the pic16c5x oscillator design requires the use of a parallel cut crystal. use of a series cut crystal may give a frequency out of the crystal manufacturers speci?ations. when in xt, lp or hs modes, the device can have an external clock source drive the osc1/clkin pin (figure 7-3). figure 7-2: crystal operation or ceramic resonator (hs, xt or lp osc configuration) figure 7-3: external clock input operation (hs, xt or lp osc configuration) note 1: see capacitor selection tables for recommended values of c1 and c2. 2: a series resistor (rs) may be required for at strip cut crystals. 3: rf varies with the crystal chosen (approx. value = 10 m w ). c1 (1) c2 (1) xtal osc2 osc1 rf (3) sleep to internal logic rs (2) pic16c5x clock from ext. system osc1 osc2 pic16c5x open
1995 microchip technology inc. ds30015m-page 29 pic16c5x preliminary 7.2.3 external crystal oscillator circuit either a prepackaged oscillator or a simple oscillator circuit with ttl gates can be used as an external crystal oscillator circuit. prepackaged oscillators provide a wide operating range and better stability. a well-designed crystal oscillator will provide good performance with ttl gates. two types of crystal oscillator circuits can be used: one with parallel resonance, or one with series resonance. figure 7-4 shows implementation of a parallel resonant oscillator circuit. the circuit is designed to use the fundamental frequency of the crystal. the 74as04 inverter performs the 180-degree phase shift that a parallel oscillator requires. the 4.7 k w resistor provides the negative feedback for stability. the 10 k w potentiometers bias the 74as04 in the linear region. this circuit could be used for external oscillator designs. figure 7-4: external parallel resonant crystal oscillator circuit figure 7-5 shows a series resonant oscillator circuit. this circuit is also designed to use the fundamental frequency of the crystal. the inverter performs a 180-degree phase shift in a series resonant oscillator circuit. the 330 w resistors provide the negative feedback to bias the inverters in their linear region. figure 7-5: external series resonant crystal oscillator circuit 20 pf +5v 20 pf 10k 4.7k 10k 74as04 xtal 10k 74as04 pic16c5x clkin to other devices 330 74as04 74as04 pic16c5x clkin to other devices xtal 330 74as04 0.1 m f table 7-3: capacitor selection for ceramic resonators - pic16cr54 table 7-4: capacitor selection for crystal oscillator - pic16cr54 osc type resonator freq cap. range c1 cap. range c2 data not available at this time. osc type resonator freq cap.range c1 cap. range c2 lp 32 khz (1) 100 khz 200 khz 15-33 pf 15-33 pf 15-30 pf 15-33 pf 15-33 pf 15-30 pf xt 100 khz 200 khz 1 mhz 2 mhz 4 mhz 68-100 pf 15-30 pf 15-47 pf 15-47 pf 15-47 pf 68-100 pf 15-30 pf 15-47 pf 15-47 pf 15-47 pf hs 4 mhz 8 mhz 20 mhz 15-47 pf 15-47 pf 15-47 pf 15-47 pf 15-47 pf 15-47 pf note 1: for v dd < 2.5v, c1 = c2 ? 15-33pf is recommended. these values are for design guidance only. rs may be required in hs mode as well as xt mode to avoid overdriving crystals with low drive level speci?ation. since each crystal has its own characteristics, the user should consult the crystal manufacturer for appropriate values of external components.
pic16c5x ds30015m-page 30 1995 microchip technology inc. 7.2.4 rc oscillator for timing insensitive applications, the rc device option offers additional cost savings. the rc oscillator frequency is a function of the supply voltage, the resistor (rext) and capacitor (cext) values, and the operating temperature. in addition to this, the oscillator frequency will vary from unit to unit due to normal process parameter variation. furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low cext values. the user also needs to take into account variation due to tolerance of external r and c components used. figure 7-6 shows how the r/c combination is connected to the pic16c5x. for rext values below 2.2 k w , the oscillator operation may become unstable, or stop completely. for very high rext values (e.g., 1 m w ) the oscillator becomes sensitive to noise, humidity and leakage. thus, we recommend keeping rext between 3 k w and 100 k w . although the oscillator will operate with no external capacitor (cext = 0 pf), we recommend using values above 20 pf for noise and stability reasons. with no or small external capacitance, the oscillation frequency can vary dramatically due to changes in external capacitances, such as pcb trace capacitance or package lead frame capacitance. the electrical speci?ations sections show rc frequency variation from part to part due to normal process variation. the variation is larger for larger r (since leakage current variation will affect rc frequency more for large r) and for smaller c (since variation of input capacitance will affect rc frequency more). also, see the electrical speci?ations sections for variation of oscillator frequency due to v dd for given rext/cext values as well as frequency variation due to operating temperature for given r, c, and v dd values. the oscillator frequency, divided by four, is available on the osc2/clkout pin, and can be used for test purposes or to synchronize other logic. figure 7-6: rc oscillator mode v dd rext cext v ss osc1 internal clock osc2/clkout fosc/4 pic16c5x n 7.3 reset pic16c5x devices may be reset in one of the following ways: power-on reset (por) ? clr reset (normal operation) mclr wake-up reset (from sleep) wdt reset (normal operation) wdt wake-up reset (from sleep) table 7-5 shows these reset conditions for the pcl and status registers. some registers are not affected in any reset condition. their status is unknown on por and unchanged in any other reset. most other registers are reset to a ?eset state?on power-on reset (por), mclr or wdt reset. a mclr or wdt wake-up from sleep also results in a device reset, and not a continuation of operation before sleep. the t o and pd bits (status <4:3>) are set or cleared depending on the different reset conditions (section 7.7). these bits may be used to determine the nature of the reset. table 7-6 lists a full description of reset states of all registers. figure 7-7 shows a simpli?d block diagram of the on-chip reset circuit.
1995 microchip technology inc. ds30015m-page 31 pic16c5x table 7-5: reset conditions for special registers table 7-6: reset conditions for all registers figure 7-7: simplified block diagram of on-chip reset circuit condition pcl addr: 02h status addr: 03h power-on reset 1111 1111 0001 1xxx m clr reset (normal operation) 1111 1111 000u uuuu (1) mclr wake-up (from sleep) 1111 1111 0001 0uuu wdt reset (normal operation) 1111 1111 0000 1uuu (2) wdt wake-up (from sleep) 1111 1111 0000 0uuu legend: u = unchanged, x = unknown, - = unimplemented read as '0'. note 1: t o and pd bits retain their last value until one of the other reset conditions occur. 2: the clrwdt instruction will set the t o and pd bits. register address power-on reset mclr or wdt reset w n/a xxxx xxxx uuuu uuuu tris n/a 1111 1111 1111 1111 option n/a --11 1111 --11 1111 indf 00h xxxx xxxx uuuu uuuu tmr0 01h xxxx xxxx uuuu uuuu pcl (1) 02h 1111 1111 1111 1111 status (1) 03h 0001 1xxx 000q quuu fsr 04h 1xxx xxxx 1uuu uuuu porta 05h ---- xxxx ---- uuuu portb 06h xxxx xxxx uuuu uuuu portc (2) 07h xxxx xxxx uuuu uuuu general purpose register ?es 08-7fh xxxx xxxx uuuu uuuu legend: u = unchanged, x = unknown, - = unimplemented, read as '0', q = see tables in section 7.7 for possible values. note 1: see table 7-5 for reset value for speci? conditions. 2: general purpose register ?e on the pic16c54/cr54/c56. sq r q v dd mclr /v pp pin power-up detect on-chip rc osc por (power-on reset) wdt time-out reset chip reset 8-bit asynch ripple counter (start-up timer)
pic16c5x ds30015m-page 32 1995 microchip technology inc. 7.4 p o wer -on reset (por) the pic16c5x family incorporates on-chip power-on reset (por) circuitry which provides an internal chip reset for most power-up situations. to use this feature, the user merely ties the mclr /v pp pin (figure 7-8) to v dd . a simpli?d block diagram of the on-chip power-on reset circuit is shown in figure 7-7. the power-on reset circuit and the device reset timer (section 7.5) circuit are closely related. on power-up, the reset latch is set and the drt is reset. the drt timer begins counting once it detects mclr to be high. after the time-out period, which is typically 18 ms, it will reset the reset latch and thus end the on-chip reset signal. a power-up example where mclr is not tied to v dd is shown in figure 7-10. v dd is allowed to rise and stabilize before bringing mclr high. the chip will actually come out of reset t drt msec after mclr goes high. in figure 7-11, the on-chip power-on reset feature is being used (mclr and v dd are tied together). the v dd is stable before the start-up timer times out and there is no problem in getting a proper reset. however, figure 7-12 depicts a problem situation where v dd rises too slowly. the time between when the drt senses a high on the mclr /v pp pin, and when the mclr /v pp pin (and v dd ) actually reach their full value, is too long. in this situation, when the start-up timer times out, v dd has not reached the v dd (min) value and the chip is, therefore, not guaranteed to function correctly. on-chip por is guaranteed to work if the rate of rise of v dd is no slower than 0.05v/ms and v dd starts from 0v. if the on-chip por time delay is too short for low frequency crystals/resonators (which require much longer than 18 ms to start-up and stabilize) or for high frequency crystals/resonators (which have to reach a higher v dd voltage for operation), we recommend that external rc circuits be used to achieve longer por delay times (figure 7-9). figure 7-8: electrical structure of mclr /v pp pin figure 7-9: external power-on reset circuit (for slow v dd power-up) v ss v ss r in schmitt trigger mclr n input buffer pin note 1: esd protection circuits (1) (1) external power-on reset circuit is required only if v dd power-up is too slow. the diode d helps discharge the capacitor quickly when v dd powers down. r < 40 k w is recommended to make sure that voltage drop across r does not exceed 0.2v (max leakage current spec on mclr/ v pp pin is 5 m a). a larger voltage drop will degrade v ih level on mclr/ v pp pin. r1 = 100 w to 1 k w will limit any current ?wing into mclr from external capacitor c in the event of mclr pin breakdown due to esd or eos. c r1 r d mclr pic16c5x v dd v dd
1995 microchip technology inc. ds30015m-page 33 pic16c5x figure 7-10: time-out sequence on power-up (mclr not tied to v dd ) figure 7-11: time-out sequence on power-up (mclr tied to v dd ): fast v dd rise time figure 7-12: time-out sequence on power-up (mclr tied to v dd ): slow v dd rise time v dd mclr internal por drt time-out internal reset t drt v dd mclr internal por drt time-out internal reset t drt v dd mclr internal por drt time-out internal reset t drt v1 when v dd rises slowly, the t drt time-out expires long before v dd has reached its ?al value. in this example, the chip will reset properly if, and only if, v1 3 v dd min.
pic16c5x ds30015m-page 34 1995 microchip technology inc. 7.5 de vice reset ti mer (dr t) the device reset timer (drt) provides a ?ed 18 ms nominal time-out on reset. the drt operates on an internal rc oscillator. the processor is kept in reset as long as the drt is active. the drt delay allows v dd to rise above v dd min., and for the oscillator to stabilize. oscillator circuits based on crystals or ceramic resonators require a certain time after power-up to establish a stable oscillation. the on-chip drt keeps the device in a reset for approximately 18 ms after the voltage on the mclr /v pp pin has reached a logic high (v ihmc ) level. thus, external rc networks connected to the mclr input are not required in most cases, allowing for savings in cost-sensitive and/or space restricted applications. the device reset time delay will vary from chip to chip due to v dd , temperature, and process variation. see ac parameters for details. the drt will also be triggered upon a watchdog timer time-out. this is particularly important for applications using the wdt to wake the pic16c5x from sleep mode automatically. 7.6 w atc hdog timer (wdt) the watchdog timer (wdt) is a free running on-chip rc oscillator which does not require any external components. this rc oscillator is separate from the rc oscillator of the osc1/clkin pin. that means that the wdt will run even if the clock on the osc1/clkin and osc2/clkout pins have been stopped, for example, by execution of a sleep instruction. during normal operation or sleep, a wdt reset or wake-up reset generates a device reset. the t o bit (status<4>) will be cleared upon a watchdog timer reset. the wdt can be permanently disabled by programming the con?uration bit wdte as a '0' (section 7.1). 7.6.1 wdt period the wdt has a nominal time-out period of 18 ms, (with no prescaler). if a longer time-out period is desired, a prescaler with a division ratio of up to 1:128 can be assigned to the wdt (under software control) by writing to the option register. thus, time-out a period of a nominal 2.3 seconds can be realized. these periods vary with temperature, v dd and part-to-part process variations (see dc specs). under worst case conditions (v dd = min., temperature = max., max. wdt prescaler), it may take several seconds before a wdt time-out occurs. 7.6.2 wdt programming considerations the clrwdt instruction clears the wdt and the postscaler, if assigned to the wdt, and prevents it from timing out and generating a device reset. the sleep instruction resets the wdt and the postscaler, if assigned to the wdt. this gives the maximum sleep time before a wdt wake-up reset.
1995 microchip technology inc. ds30015m-page 35 pic16c5x figure 7-13: watchdog timer block diagram table 7-7: summary of registers associated with the watchdog timer address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on power-on reset value on mclr and wdt reset fffh (1) con?. word (2) cp wdte fosc1 fosc0 ---- uuuu ---- uuuu n/a option t0cs t0se psa ps2 ps1 ps0 --11 1111 --11 1111 legend: shaded boxes = not used by watchdog timer, = unimplemented, read as '0', u = unchanged note 1: refer to the pic16c5x programming speci?ations (literature number ds30190) to determine how to access the con?u- ration word. 2: only the ?st 8 bits of the con?uration word are shown. reset values (for por, mclr and wdt) for bits 12:8 are unim- plemented, read as ?? initial values of bits 3:0 = 1111 . 1 0 1 0 from timer0 clock source (figure 6-6) to timer0 (figure 6-6) postscaler wdt enable eprom bit psa wdt time-out ps2:ps0 psa mux 8 - to - 1 mux postscaler m u x watchdog timer note: t0cs, t0se, psa, ps2:ps0 are bits in the option register.
pic16c5x ds30015m-page 36 1995 microchip technology inc. 7.7 time-out sequence and p o wer do wn status bits ( t o / pd ) the t o and pd bits in the status register can be tested to determine if a reset condition has been caused by a power-up condition, a mclr or watchdog timer (wdt) reset, or a mclr or wdt wake-up reset. these status bits are only affected by events listed in table 7-9. table 7-5 lists the reset conditions for the special function registers, while table 7-6 lists the reset conditions for all the registers. table 7-8: t o /pd status after reset t o pd reset was caused by 11 power-up (por) uu mclr reset (normal operation) (1) 10 mclr wake-up reset (from sleep) 01 wdt reset (normal operation) 00 wdt wake-up reset (from sleep) legend: u = unchanged note 1: the t o and pd bits maintain their status ( u ) until a reset occurs. a low-pulse on the mclr input does not change the t o and pd status bits. table 7-9: events affecting t o /pd status bits event t o pd remarks power-up 11 wdt time-out 0u no effect on pd sleep instruction 10 clrwdt instruction 11 legend: u = unchanged a wdt time-out will occur regardless of the status of the t o bit. a sleep instruction will be executed, regardless of the status of the pd bit. table 7-8 re?cts the status of t o and pd after the corresponding event. 7.8 reset on br o wn-out a brown-out is a condition where device power (v dd ) dips below its minimum value, but not to zero, and then recovers. the device should be reset in the event of a brown-out. to reset pic16c5x devices when a brown-out occurs, external brown-out protection circuits may be built (figure 7-14 and figure 7-15). figure 7-14: brown-out protection circuit 1 figure 7-15: brown-out protection circuit 2 this circuit will activate reset when v dd goes below vz + 0.7v (where vz = zener voltage). 33k 10k 40k v dd mclr pic16c5x v dd this brown-out circuit is less expensive, although less accurate. transistor q1 turns off when v dd is below a certain level such that: v dd r1 r1 + r2 = 0.7v r2 40k v dd mclr pic16c5x r1 q1 v dd
1995 microchip technology inc. ds30015m-page 37 pic16c5x 7.9 p o wer -do wn mode (sleep) a device may be powered down (sleep) and later powered up (wake-up from sleep). 7.9.1 sleep the power-down mode is entered by executing a sleep instruction. if enabled, the watchdog timer will be cleared but keeps running, the t o bit (status<4>) is set, the pd bit (status<3>) is cleared and the oscillator driver is turned off. the i/o ports maintain the status they had before the sleep instruction was executed (driving high, driving low, or hi-impedance). it should be noted that a reset generated by a wdt time-out does not drive the mclr /v pp pin low. for lowest current consumption while powered down, the t0cki input should be at v dd or v ss and the mclr /v pp pin must be at a logic high level (v ihmc ). 7.9.2 wake-up from sleep the device can wake-up from sleep through one of the following events: 1. an external reset input on mclr /v pp pin. 2. a watchdog timer time-out reset (if wdt was enabled). both of these events cause a device reset. the t o and pd bits can be used to determine the cause of device reset. the t o bit is cleared if a wdt time-out occurred (and caused wake-up). the pd bit, which is set on power-up, is cleared when sleep is invoked. the wdt is cleared when the device wakes from sleep, regardless of the wake-up source. 7.10 code pr otection the program memory can be code protected by selecting the code protect option when programming the device. in a code protected mode, the con?uration word will not be protected, allowing reading of all bits. for eprom devices, program memory locations 40h and above cannot be further programmed. however, the ?st 64 locations, 00h-3fh, may be programmed. these locations are not considered "secure". 7.11 id locations four memory locations are designated as id locations where the user can store checksum or other code-identi?ation numbers. these locations are not accessible during normal execution but are readable and writable during program/verify. use only the lower four bits of the id locations and always program the upper eight bits as '1's. note: microchip will assign a unique pattern number for qtp and sqtp requests and for rom devices. this pattern number will be unique and traceable to the submitted code.
pic16c5x ds30015m-page 38 1995 microchip technology inc. notes:
1995 microchip technology inc. ds30015m-page 39 pic16c5x 8.0 instruction set summary each pic16c5x instruction is a 12-bit word divided into an opcode, which speci?s the instruction type, and one or more operands which further specify the operation of the instruction. the pic16c5x instruction set summary in table 8-2 groups the instructions into byte-oriented, bit-oriented, and literal and control operations. table 8-1 shows the opcode ?ld descriptions. for byte-oriented instructions, 'f' represents a ?e register designator and 'd' represents a destination designator. the ?e register designator is used to specify which one of the 32 file registers is to be used by the instruction. the destination designator speci?s where the result of the operation is to be placed. if 'd' is '0', the result is placed in the w register. if 'd' is '1', the result is placed in the ?e register speci?d in the instruction. for bit-oriented instructions, 'b' represents a bit ?ld designator which selects the number of the bit affected by the operation, while 'f' represents the number of the ?e in which the bit is located. for literal and control operations, 'k' represents an 8 or 9-bit constant or literal value. table 8-1: opcode field descriptions field description f register ?e address (0x00 to 0x7f) w working register (accumulator) b bit address within an 8-bit ?e register k literal ?ld, constant data or label x don't care location (= 0 or 1) the assembler will generate code with x = 0. it is the recommended form of use for compatibility with all microchip software tools. d destination select; d = 0 (store result in w) d = 1 (store result in ?e register 'f') default is d = 1 label label name tos top of stack pc program counter wdt watchdog timer counter to time-out bit pd power-down bit dest destination, either the w register or the speci?d register ?e location [ ] options ( ) contents assigned to < > register bit ?ld in the set of i talics user de?ed term (font is courier) all instructions are executed within one single instruction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction. in this case, the execution takes two instruction cycles. one instruction cycle consists of four oscillator periods. thus, for an oscillator frequency of 4 mhz, the normal instruction execution time is 1 m s. if a conditional test is true or the program counter is changed as a result of an instruction, the instruction execution time is 2 m s. figure 8-1 shows the three general formats that the instructions can have. all examples in the ?ure use the following format to represent a hexadecimal number: 0xhhh where 'h' signi?s a hexadecimal digit. figure 8-1: general format for instructions byte-oriented ?e register operations 11 6 5 4 0 d = 0 for destination w opcode d f (file #) d = 1 for destination f f = 5-bit ?e register address bit-oriented ?e register operations 11 8 7 5 4 0 opcode b (bit #) f (file #) b = 3-bit bit address f = 5-bit ?e register address literal and control operations (except goto ) 11 8 7 0 opcode k (literal) k = 8-bit immediate value literal and control operations - goto instruction 11 9 8 0 opcode k (literal) k = 9-bit immediate value this document was created with framemake r404
pic16c5x ds30015m-page 40 1995 microchip technology inc. table 8-2: instruction set summary mnemonic, operands description cycles 12-bit opcode status affected notes msb lsb addwf andwf clrf clrw comf decf decfsz incf incfsz iorwf movf movwf nop rlf rrf subwf swapf xorwf f,d f,d f f, d f, d f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d add w and f and w with f clear f clear w complement f decrement f decrement f, skip if 0 increment f increment f, skip if 0 inclusive or w with f move f move w to f no operation rotate left f through carry rotate right f through carry subtract w from f swap f exclusive or w with f 1 1 1 1 1 1 1(2) 1 1(2) 1 1 1 1 1 1 1 1 1 0001 0001 0000 0000 0010 0000 0010 0010 0011 0001 0010 0000 0000 0011 0011 0000 0011 0001 11df 01df 011f 0100 01df 11df 11df 10df 11df 00df 00df 001f 0000 01df 00df 10df 10df 10df ffff ffff ffff 0000 ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff c,dc,z z z z z z none z none z z none none c c c,dc,z none z 1,2,4 2,4 4 2,4 2,4 2,4 2,4 2,4 2,4 1,4 2,4 2,4 1,2,4 2,4 2,4 bit-oriented file register operations bcf bsf btfsc btfss f, b f, b f, b f, b bit clear f bit set f bit test f, skip if clear bit test f, skip if set 1 1 1 (2) 1 (2) 0100 0101 0110 0111 bbbf bbbf bbbf bbbf ffff ffff ffff ffff none none none none 2,4 2,4 literal and control operations andlw call clrwdt goto iorlw movlw option retlw sleep tris xorlw k k k k k k k k f k and literal with w call subroutine clear watchdog timer unconditional branch inclusive or literal with w move literal to w load option register return, place literal in w go into standby mode load tris register exclusive or literal to w 1 2 1 2 1 1 1 2 1 1 1 1110 1001 0000 101k 1101 1100 0000 1000 0000 0000 1111 kkkk kkkk 0000 kkkk kkkk kkkk 0000 kkkk 0000 0000 kkkk kkkk kkkk 0100 kkkk kkkk kkkk 0010 kkkk 0011 0fff kkkk z none t o , pd none z none none none t o , pd none z 1 3 note 1: the 9th bit of the program counter will be forced to a '0' by any instruction that writes to the pc except for goto . (section 4.5) 2: when an i/o register is modi?d as a function of itself (e.g. movf portb, 1 ), the value used will be that value present on the pins themselves. for example, if the data latch is '1' for a pin con?ured as input and is driven low by an external device, the data will be written back with a '0'. 3: the instruction tris f , where f = 5, 6, or 7 causes the contents of the w register to be written to the tristate latches of porta, b or c, respectively. a '1' forces the pin to a hi-impedance state and disables the output buff- ers. 4: if this instruction is executed on the tmr0 register (and, where applicable, d = 1), the prescaler will be cleared (if assigned to tmr0).
1995 microchip technology inc. ds30015m-page 41 pic16c5x addwf add w and f syntax: [ label ] addwf f,d operands: 0 f 31 d ?[0,1] operation: (w) + (f) (dest) status affected: c, dc, z encoding: 0001 11df ffff description: add the contents of the w register and register 'f'. if 'd' is 0 the result is stored in the w register. if 'd' is '1' the result is stored back in register 'f' . words: 1 cycles: 1 example: addwf fsr, 0 before instruction w = 0x17 fsr = 0xc2 after instruction w = 0xd9 fsr = 0xc2 andlw and literal with w syntax: [ label ] andlw k operands: 0 k 255 operation: (w).and. (k) (w) status affected: z encoding: 1110 kkkk kkkk description: the contents of the w register are and?d with the eight-bit literal 'k'. the result is placed in the w register . words: 1 cycles: 1 example: andlw 0x5f before instruction w = 0xa3 after instruction w = 0x03 andwf and w with f syntax: [ label ] andwf f,d operands: 0 f 31 d ?[0,1] operation: (w) .and. (f) (dest) status affected: z encoding: 0001 01df ffff description: the contents of the w register are and?d with register 'f'. if 'd' is 0 the result is stored in the w register. if 'd' is '1' the result is stored back in register 'f' . words: 1 cycles: 1 example: andwf fsr, 1 before instruction w = 0x17 fsr = 0xc2 after instruction w = 0x17 fsr = 0x02 bcf bit clear f syntax: [ label ] bcf f,b operands: 0 f 31 0 b 7 operation: 0 (f) status affected: none encoding: 0100 bbbf ffff description: bit 'b' in register 'f' is cleared. words: 1 cycles: 1 example: bcf flag_reg, 7 before instruction flag_reg = 0xc7 after instruction flag_reg = 0x47
pic16c5x ds30015m-page 42 1995 microchip technology inc. bsf bit set f syntax: [ label ] bsf f,b operands: 0 f 31 0 b 7 operation: 1 (f) status affected: none encoding: 0101 bbbf ffff description: bit 'b' in register 'f' is set. words: 1 cycles: 1 example: bsf flag_reg, 7 before instruction flag_reg = 0x0a after instruction flag_reg = 0x8a btfsc bit test f, skip if clear syntax: [ label ] btfsc f,b operands: 0 f 31 0 b 7 operation: skip if (f) = 0 status affected: none encoding: 0110 bbbf ffff description: if bit 'b' in register 'f' is 0 then the next instruction is skipped. if bit 'b' is 0 then the next instruction fetched during the current instruction execution is discarded, and an nop is executed instead, making this a 2 cycle instruction. words: 1 cycles: 1(2) example: here false true btfsc goto flag,1 process_code before instruction pc = address (here) after instruction if flag<1> = 0, pc = address (true) ; if flag<1> = 1, pc = address (false) btfss bit test f, skip if set syntax: [ label ] btfss f,b operands: 0 f 31 0 b < 7 operation: skip if (f) = 1 status affected: none encoding: 0111 bbbf ffff description: if bit 'b' in register 'f' is '1' then the next instruction is skipped. if bit 'b' is '1', then the next instruction fetched during the current instruction execution, is discarded and an nop is executed instead, making this a 2 cycle instruction. words: 1 cycles: 1(2) example: here btfss flag,1 false goto process_code true ? ? before instruction pc = address (here) after instruction if flag<1> = 0, pc = address (false) ; if flag<1> = 1, pc = address (true)
1995 microchip technology inc. ds30015m-page 43 pic16c5x call subroutine call syntax: [ label ] call k operands: 0 k 255 operation: (pc) + 1 top of stack; k pc<7:0>; (status<6:5>) pc<10:9>; 0 pc<8> status affected: none encoding: 1001 kkkk kkkk description: subroutine call. first, return address (pc+1) is pushed onto the stack. the eight bit immediate address is loaded into pc bits <7:0>. the upper bits pc<10:9> are loaded from sta- tus<6:5>, pc<8> is cleared. call is a two cycle instruction. words: 1 cycles: 2 example: here call there before instruction pc = address (here) after instruction pc = address (there) tos = address (here + 1) clrf clear f syntax: [ label ] clrf f operands: 0 f 31 operation: 00h (f); 1 z status affected: z encoding: 0000 011f ffff description: the contents of register 'f' are cleared and the z bit is set. words: 1 cycles: 1 example: clrf flag_reg before instruction flag_reg = 0x5a after instruction flag_reg = 0x00 z=1 clrw clear w syntax: [ label ] clrw operands: none operation: 00h (w); 1 z status affected: z encoding: 0000 0100 0000 description: the w register is cleared. zero bit (z) is set. words: 1 cycles: 1 example: clrw before instruction w = 0x5a after instruction w = 0x00 z=1 clrwdt clear watchdog timer syntax: [ label ] clrwdt operands: none operation: 00h wdt; 0 wdt prescaler (if assigned); 1 t o; 1 pd status affected: t o , pd encoding: 0000 0000 0100 description: the clrwdt instruction resets the wdt. it also resets the prescaler, if the prescaler is assigned to the wdt and not timer0. status bits t o and pd are set. words: 1 cycles: 1 example: clrwdt before instruction wdt counter = ? after instruction wdt counter = 0x00 wdt prescale = 0 t o =1 pd =1
pic16c5x ds30015m-page 44 1995 microchip technology inc. comf complement f syntax: [ label ] comf f,d operands: 0 f 31 d [0,1] operation: (f ) (dest) status affected: z encoding: 0010 01df ffff description: the contents of register 'f' are comple- mented. if 'd' is 0 the result is stored in the w register. if 'd' is 1 the result is stored back in register 'f'. words: 1 cycles: 1 example: comf reg1,0 before instruction reg1 = 0x13 after instruction reg1 = 0x13 w = 0xec decf decrement f syntax: [ label ] decf f,d operands: 0 f 31 d [0,1] operation: (f) ?1 (dest) status affected: z encoding: 0000 11df ffff description: decrement register 'f'. if 'd' is 0 the result is stored in the w register. if 'd' is 1 the result is stored back in register 'f'. words: 1 cycles: 1 example: decf cnt, 1 before instruction cnt = 0x01 z=0 after instruction cnt = 0x00 z=1 decfsz decrement f, skip if 0 syntax: [ label ] decfsz f,d operands: 0 f 31 d [0,1] operation: (f) ?1 d; skip if result = 0 status affected: none encoding: 0010 11df ffff description: the contents of register 'f' are decre- mented. if 'd' is 0 the result is placed in the w register. if 'd' is 1 the result is placed back in register 'f'. if the result is 0, the next instruction, which is already fetched, is discarded and an nop is executed instead mak- ing it a two cycle instruction. words: 1 cycles: 1(2) example: here decfsz cnt, 1 goto loop continue before instruction pc = address (here) after instruction cnt = cnt - 1; if cnt = 0, pc = address (continue) ; if cnt 0, pc = address (here+1) goto unconditional branch syntax: [ label ] goto k operands: 0 k 511 operation: k pc<8:0>; status<6:5> pc<10:9> status affected: none encoding: 101k kkkk kkkk description: goto is an unconditional branch. the 9-bit immediate value is loaded into pc bits <8:0>. the upper bits of pc are loaded from status<6:5>. goto is a two cycle instruction. words: 1 cycles: 2 example: goto there after instruction pc = address (there)
1995 microchip technology inc. ds30015m-page 45 pic16c5x incf increment f syntax: [ label ] incf f,d operands: 0 f 31 d [0,1] operation: (f) + 1 (dest) status affected: z encoding: 0010 10df ffff description: the contents of register 'f' are incre- mented. if 'd' is 0 the result is placed in the w register. if 'd' is 1 the result is placed back in register 'f'. words: 1 cycles: 1 example: incf cnt, 1 before instruction cnt = 0xff z=0 after instruction cnt = 0x00 z=1 incfsz increment f, skip if 0 syntax: [ label ] incfsz f,d operands: 0 f 31 d [0,1] operation: (f) + 1 (dest), skip if result = 0 status affected: none encoding: 0011 11df ffff description: the contents of register 'f' are incre- mented. if 'd' is 0 the result is placed in the w register. if 'd' is 1 the result is placed back in register 'f'. if the result is 0, then the next instruc- tion, which is already fetched, is dis- carded and an nop is executed instead making it a two cycle instruc- tion. words: 1 cycles: 1(2) example: here incfsz cnt, 1 goto loop continue before instruction pc = address (here) after instruction cnt = cnt + 1; if cnt = 0, pc = address (continue) ; if cnt 0, pc = address (here +1) iorlw inclusive or literal with w syntax: [ label ] iorlw k operands: 0 k 255 operation: (w) .or. (k) (w) status affected: z encoding: 1101 kkkk kkkk description: the contents of the w register are or?d with the eight bit literal 'k'. the result is placed in the w register. words: 1 cycles: 1 example: iorlw 0x35 before instruction w = 0x9a after instruction w = 0xbf z=0 iorwf inclusive or w with f syntax: [ label ] iorwf f,d operands: 0 f 31 d [0,1] operation: (w).or. (f) (dest) status affected: z encoding: 0001 00df ffff description: inclusive or the w register with regis- ter 'f'. if 'd' is 0 the result is placed in the w register. if 'd' is 1 the result is placed back in register 'f'. words: 1 cycles: 1 example: iorwf result, 0 before instruction result = 0x13 w = 0x91 after instruction result = 0x13 w = 0x93 z=0
pic16c5x ds30015m-page 46 1995 microchip technology inc. movf move f syntax: [ label ] movf f,d operands: 0 f 31 d [0,1] operation: (f) (dest) status affected: z encoding: 0010 00df ffff description: the contents of register 'f' is moved to destination 'd'. if 'd' is 0, destination is the w register. if 'd' is 1, the destination is ?e register 'f'. 'd' is 1 is useful to test a ?e register since status ?g z is affected. words: 1 cycles: 1 example: movf fsr, 0 after instruction w = value in fsr register movlw move literal to w syntax: [ label ] movlw k operands: 0 k 255 operation: k (w) status affected: none encoding: 1100 kkkk kkkk description: the eight bit literal 'k' is loaded into the w register. the don? cares will assem- ble as 0s. words: 1 cycles: 1 example: movlw 0x5a after instruction w = 0x5a movwf move w to f syntax: [ label ] movwf f operands: 0 f 31 operation: (w) (f) status affected: none encoding: 0000 001f ffff description: move data from the w register to regis- ter 'f' . words: 1 cycles: 1 example: movwf temp_reg before instruction temp_reg = 0xff w = 0x4f after instruction temp_reg = 0x4f w = 0x4f nop no operation syntax: [ label ] nop operands: none operation: no operation status affected: none encoding: 0000 0000 0000 description: no operation. words: 1 cycles: 1 example: nop
1995 microchip technology inc. ds30015m-page 47 pic16c5x option load option register syntax: [ label ] option operands: none operation: (w) option status affected: none encoding: 0000 0000 0010 description: the content of the w register is loaded into the option register. words: 1 cycles: 1 example option before instruction w = 0x07 after instruction option = 0x07 retlw return with literal in w syntax: [ label ] retlw k operands: 0 k 255 operation: k (w); tos pc status affected: none encoding: 1000 kkkk kkkk description: the w register is loaded with the eight bit literal 'k'. the program counter is loaded from the top of the stack (the return address). this is a two cycle instruction. words: 1 cycles: 2 example: table call table ;w contains ;table offset ;value. ? ;w now has table ? ;value. addwf pc ;w = offset retlw k1 ;begin table retlw k2 ; retlw kn ; end of table before instruction w = 0x07 after instruction w = value of k8 rlf rotate left f through carry syntax: [ label ] rlf f,d operands: 0 f 31 d [0,1] operation: see description below status affected: c encoding: 0011 01df ffff description: the contents of register 'f' are rotated one bit to the left through the carry flag. if 'd' is 0 the result is placed in the w register. if 'd' is 1 the result is stored back in register 'f'. words: 1 cycles: 1 example: rlf reg1,0 before instruction reg1 = 1110 0110 c= 0 after instruction reg1 = 1110 0110 w= 1100 1100 c= 1 rrf rotate right f through carry syntax: [ label ] rrf f,d operands: 0 f 31 d [0,1] operation: see description below status affected: c encoding: 0011 00df ffff description: the contents of register 'f' are rotated one bit to the right through the carry flag. if 'd' is 0 the result is placed in the w register. if 'd' is 1 the result is placed back in register 'f'. words: 1 cycles: 1 example: rrf reg1,0 before instruction reg1 = 1110 0110 c= 0 after instruction reg1 = 1110 0110 w= 0111 0011 c= 0 c register 'f' c register 'f'
pic16c5x ds30015m-page 48 1995 microchip technology inc. sleep enter sleep mode syntax: [ label ] sleep operands: none operation: 00h wdt; 0 wdt prescaler; 1 t o ; 0 pd status affected: t o , pd encoding: 0000 0000 0011 description: time-out status bit (t o ) is set. the power down status bit (pd ) is cleared. the wdt and its prescaler are cleared. the processor is put into sleep mode with the oscillator stopped. see sec- tion on sleep for more details. words: 1 cycles: 1 example: sleep subwf subtract w from f syntax: [ label ] subwf f,d operands: 0 ? f ? 31 d [0,1] operation: (f) ?(w) ( dest) status affected: c, dc, z encoding: 0000 10df ffff description: subtract (2s complement method) the w register from register 'f'. if 'd' is 0 the result is stored in the w register. if 'd' is 1 the result is stored back in register 'f'. words: 1 cycles: 1 example 1 : subwf reg1, 1 before instruction reg1 = 3 w=2 c=? after instruction reg1 = 1 w=2 c = 1 ; result is positive e xample 2 : before instruction reg1 = 2 w=2 c=? after instruction reg1 = 0 w=2 c = 1 ; result is zero e xample 3 : before instruction reg1 = 1 w=2 c=? after instruction reg1 = ff w=2 c = 0 ; result is negative
1995 microchip technology inc. ds30015m-page 49 pic16c5x swapf swap nibbles in f syntax: [ label ] swapf f,d operands: 0 f 31 d [0,1] operation: (f<3:0>) (dest<7:4>); (f<7:4>) (dest<3:0>) status affected: none encoding: 0011 10df ffff description: the upper and lower nibbles of register 'f' are exchanged. if 'd' is 0 the result is placed in w register. if 'd' is 1 the result is placed in register 'f'. words: 1 cycles: 1 example swapf reg1, 0 before instruction reg1 = 0xa5 after instruction reg1 = 0xa5 w = 0x5a tris load tris register syntax: [ label ] tris f operands: f = 5, 6 or 7 operation: (w) tris register f status affected: none encoding: 0000 0000 0fff description: tris register 'f' (f = 5, 6, or 7) is loaded with the contents of the w register words: 1 cycles: 1 example tris porta before instruction w = 0xa5 after instruction trisa = 0xa5 xorlw exclusive or literal with w syntax: [ label ] xorlw k operands: 0 ? k ? 255 operation: (w) .xor. k ( w) status affected: z encoding: 1111 kkkk kkkk description: the contents of the w register are xor?d with the eight bit literal 'k'. the result is placed in the w register. words: 1 cycles: 1 example: xorlw 0xaf before instruction w = 0xb5 after instruction w = 0x1a xorwf exclusive or w with f syntax: [ label ] xorwf f,d operands: 0 f 31 d [0,1] operation: (w) .xor. (f) ( dest) status affected: z encoding: 0001 10df ffff description: exclusive or the contents of the w register with register 'f'. if 'd' is 0 the result is stored in the w register. if 'd' is 1 the result is stored back in register 'f'. words: 1 cycles: 1 example xorwf reg,1 before instruction reg = 0xaf w = 0xb5 after instruction reg = 0x1a w = 0xb5
pic16c5x ds30015m-page 50 1995 microchip technology inc. notes:
1995 microchip technology inc. ds30015m-page 51 pic16c5x 9.0 development support 9.1 de velopmen t t ools the pic16/17 microcontrollers are supported with a full range of hardware and software development tools: picmaster real-time in-circuit emulator pro mate universal programmer picstart low-cost prototype programmer picdem-1 low-cost demonstration board picdem-2 low-cost demonstration board mpasm assembler mpsim software simulator c compiler (mp-c) fuzzy logic development system ( fuzzy tech - mp) 9.2 picmaster h igh p erf ormance univer sal in-cir cuit em ulator with mplab ide the picmaster universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for all microcontrollers in the pic16c5x, pic16cxx and pic17cxx families. picmaster is supplied with the mplab integrated development environment (ide), which allows editing, "make" and download, and source debugging from a single environment. a picmaster system con?uration is shown in figure 9-1. interchangeable target probes allow the system to be easily recon?ured for emulation of different proces- sors. the universal architecture of the picmaster allows expansion to support all new pic16c5x, pic16cxx and pic17cxx microcontrollers. the picmaster emulator system has been designed as a real-time emulation system with advanced features that are generally found on more expensive development tools. the pc compatible 386 (and better) machine platform and the microsoft windows 3.x environment was chosen to best make these features available to you, the end user. the picmaster universal emulator system consists primarily of four major components: host-interface card emulator control pod target-speci? emulator probe pc-host emulation control software the windows operating system allows the developer to take full advantage of the many powerful features and functions of the picmaster system. picmaster emulation can operate in one window, while a text editor is running in a second window. pc-host emulation control software takes full advan- tage of dynamic data exchange (dde), a feature of windows. dde allows data to be dynamically trans- ferred between two or more windows programs. with this feature, data collected with picmaster can be automatically transferred to a spreadsheet or database program for further analysis. under windows, as many as four picmaster emula- tors can be run simultaneously from the same pc mak- ing development of multi-microcontroller systems possible (e.g., a system containing a pic16cxx processor and a pic17cxx processor). the picmaster probes speci?ations are shown in table 9-1. figure 9-1: picmaster system configuration windows 3.x common interface card pc compatible computer power switch power connector pc-interface in-line power supply (optional) 5 vdc picmaster emulator pod interchangeable emulator probe pc bus 90 - 250 vac logic probes this document was created with framemake r404
pic16c5x ds30015m-page 52 1995 microchip technology inc. table 9-1: picmaster probe specification devices picmaster probe probe maximum frequency operating voltage pic16c54 probe-16d 20 mhz 4.5v - 5.5v pic16c54a probe-16d 20 mhz 4.5v - 5.5v pic16cr54 probe-16d 20 mhz 4.5v - 5.5v pic16cr54a probe-16d (1) 20 mhz 4.5v - 5.5v pic16cr54b probe-16d (1) 20 mhz 4.5v - 5.5v pic16c55 probe-16d 20 mhz 4.5v - 5.5v pic16cr55 probe-16d (1) 20 mhz 4.5v - 5.5v pic16c56 probe-16d 20 mhz 4.5v - 5.5v pic16cr56 probe-16d (1) 20 mhz 4.5v - 5.5v pic16c57 probe-16d 20 mhz 4.5v - 5.5v pic16cr57a probe-16d 20 mhz 4.5v - 5.5v pic16cr57b probe-16d (1) 20 mhz 4.5v - 5.5v pic16c58a probe-16d 20 mhz 4.5v - 5.5v pic16cr58a probe-16d 20 mhz 4.5v - 5.5v pic16cr58b probe-16d (1) 20 mhz 4.5v - 5.5v pic16c61 probe-16g 10 mhz 4.5v - 5.5v pic16c62 probe-16e 10 mhz 4.5v - 5.5v pic16c62a probe-16e (1) 10 mhz 4.5v - 5.5v pic16cr62 probe-16e (1) 10 mhz 4.5v - 5.5v pic16c63 probe-16f (1) 10 mhz 4.5v - 5.5v pic16c64 probe-16e 10 mhz 4.5v - 5.5v pic16c64a probe-16e (1) 10 mhz 4.5v - 5.5v pic16cr64 probe-16e (1) 10 mhz 4.5v - 5.5v pic16c65 probe-16f 10 mhz 4.5v - 5.5v pic16c65a probe-16f (1) 10 mhz 4.5v - 5.5v pic16c620 probe-16h 10 mhz 4.5v - 5.5v pic16c621 probe-16h 10 mhz 4.5v - 5.5v pic16c622 probe-16h 10 mhz 4.5v - 5.5v pic16c70 probe-16b (1) 10 mhz 4.5v - 5.5v pic16c71 probe-16b 10 mhz 4.5v - 5.5v pic16c71a probe-16b (1) 10 mhz 4.5v - 5.5v pic16c72 probe-16f (1) 10 mhz 4.5v - 5.5v pic16c73 probe-16f 10 mhz 4.5v - 5.5v pic16c73a probe-16f (1) 10 mhz 4.5v - 5.5v pic16c74 probe-16f 10 mhz 4.5v - 5.5v pic16c74a probe-16f (1) 10 mhz 4.5v - 5.5v pic16c83 probe-16c 10 mhz 4.5v - 5.5v pic16c84 probe-16c 10 mhz 4.5v - 5.5v pic17c42 probe-17b 20 mhz 4.5v - 5.5v pic17c43 probe-17b 20 mhz 4.5v - 5.5v pic17c44 probe-17b 20 mhz 4.5v - 5.5v note 1: this picmaster probe can be used to functionally emulate the device listed in the previous column. contact your microchip sales of?e for details. table 9-1: picmaster probe specification devices picmaster probe probe maximum frequency operating voltage
1995 microchip technology inc. ds30015m-page 53 pic16c5x 9.3 p r o ma te u niver sal pr ogrammer the pro mate universal programmer is a full-featured programmer capable of operating in stand-alone mode as well as pc-hosted mode. the pro mate has programmable v dd and v pp supplies which allows it to verify programmed memory at v dd min and v dd max for maximum reliability. it has an lcd display for displaying error messages, keys to enter commands and a modular detachable socket assembly to support various package types. in stand- alone mode the pro mate can read, verify or program pic16c5x, pic16cxx and pic17cxx devices. it can also set con?uration and code-protect bits in this mode. in pc-hosted mode, the pro mate connects to the pc via one of the com (rs-232) ports. pc based user-interface software makes using the programmer simple and ef?ient. the user interface is full-screen and menu-based. full screen display and editing of data, easy selection of bit con?uration and part type, easy selection of v dd min, v dd max and v pp levels, load and store to and from disk ?es (intel hex format) are some of the features of the software. essential commands such as read, verify, program and blank check can be issued from the screen. additionally, serial programming support is possible where each part is programmed with a different serial number, sequential or random. the pro mate has a modular ?rogramming socket module? different socket modules are required for different processor types and/or package types. pro mate supports all pic16c5x, pic16cxx and pic17cxx processors. 9.4 picst ar t l o w- c ost de velopment system the picstart programmer is an easy to use, very low-cost prototype programmer. it connects to the pc via one of the com (rs-232) ports. a pc-based user interface software makes using the programmer simple and ef?ient. the user interface is full-screen and menu-based. picstart is not recommended for production programming. 9.5 picdem-1 lo w-cost pic16/17 demonstration boar d the picdem-1 is a simple board which demonstrates the capabilities of several of microchips microcontrollers. the microcontrollers supported are: pic16c5x (pic16c54 to pic16c58a), pic16c61, pic16c62x, pic16c71, pic16c8x, pic17c42, pic17c43 and pic17c44. all necessary hardware and software is included to run basic demo programs. the users can program the sample micro controllers provided with the picdem-1 board, on a pro mate or picstart-16b programmer, and easily test ?mware. the user can also connect the picdem-1 board to the picmaster emulator and down load the ?mware to the emulator for testing. additional prototype area is available for the user to build some additional hardware and connect it to the microcontroller socket(s). some of the features include an rs-232 interface, a potentiometer for simulated analog input, push-button switches and eight leds connected to portb. 9.6 p icdem-2 lo w-cost pic16cxx demonstration boar d the picdem-2 is a simple demonstration board that supports the pic16c64, pic16c65, pic16c73 and pic16c74 microcon trollers. all the necessary hardware and software is included to run the basic demonstration programs. the user can program the sample microcontrollers provided with the picdem-2 board, on a pro mate programmer or picstart-16c, and easily test ?mware. the picmaster emulator may also be used with the picdem-2 board to test ?mware. additional prototype area has been provided to the user for adding additional hardware and connecting it to the microcontroller socket(s). some of the features include a rs-232 interface, push-button switches, a potentiometer for simulated analog input, a serial eeprom to demonstrate usage of the i 2 c bus and separate headers for connection to an lcd module and a keypad.
pic16c5x ds30015m-page 54 1995 microchip technology inc. 9.7 mplab integrated de velopment en vir onment software the mplab software brings an ease of software development previously unseen in the 8-bit microcontroller market. mplab is a windows based application which contains: a full featured editor three operating modes - editor - emulator - simulator (available soon) a project manager customizable tool bar and key mapping a status bar with project information extensive on-line help mplab allows you to: edit your source ?es (either assembly or "c") one touch assemble (or compile) and download to pic16/17 tools (automatically updates all project information) debug using: - source ?es - absolute listing ?e transfer data dynamically via dde (soon to be replaced by ole) run up to four emulators on the same pc the ability to use mplab with microchips simulator (available soon) allows a consistent platform and the ability to easily switch from the low cost simulator to the full featured emulator with minimal retraining due to development tools. 9.8 mp asm assemb ler the mpasm cross assembler is a pc-hosted symbolic assembler. it supports all microcontroller series including the pic16c5x, pic16cxx, and pic17cxx families. mpasm offers full featured macro capabilities, conditional assembly, and several source and listing formats. it generates various object code formats to support microchip's development tools as well as third party programmers. mpasm allows full symbolic debugging from the micro chip universal emulator system (picmaster). mpasm has the following features to assist in developing software for speci? use applications. provides translation of assembler source code to object code for all microchip microcontrollers. macro assembly capability produces all the ?es (object, listing, symbol, and special) required for symbolic debug with microchips emulator systems. supports hex (default), decimal and octal source and listing formats. mpasm provides a rich directive language to support programming of the pic16/17. directives are helpful in making the development of your assemble source code shorter and more maintainable. data directives are those that control the allocation of memory and provide a way to refer to data items symbolically (i.e., by meaningful names). control directives control the mpasm listing display. they allow the speci?ation of titles and sub-titles, page ejects and other listing control. this eases the readability of the printed output ?e. conditional directives permit sections of conditionally assembled code. this is most useful where additional functionality may wished to be added depending on the product (less functionality for the low end product, then for the high end product). also this is very helpful in the debugging of a program. macro directives control the execution and data allocation within macro body de?itions. this makes very simple the re-use of functions in a program as well as between programs.
1995 microchip technology inc. ds30015m-page 55 pic16c5x 9.9 mpsim software sim ulator the mpsim software simulator allows code development in a pc host environment. it allows the user to simulate the pic16/17 series microcontrollers on an instruction level. on any given instruction, the user may examine or modify any of the data areas or provide external stimulus to any of the pins. the input/output radix can be set by the user and the execution can be performed in; single step, execute until break, or in a trace mode. mpsim fully supports symbolic debugging using mp-c and mpasm. the software simulator offers the low cost ?xibility to develop and debug code outside of the laboratory environment making it an excellent multi-project software development tool. 9.10 mp-c c compiler the mp-c code development system is a complete 'c' compiler and integrated development environment for microchips pic16/17 family of microcontrollers. the compiler provides powerful integration capabilities and ease of use not found with other compilers. for easier source level debugging, the compiler provides symbol information that is compatible with the picmaster universal emulator memory display (picmaster emulator software versions 1.13 and later). the mp-c code development system is supplied directly by byte craft limited of waterloo, ontario, canada. if you have any questions, please contact your regional microchip fae or microchip technical support personnel at (602) 786-7627. 9.11 fuzzy tech-mp fuzzy logic de velopment system fuzzy tech-mp fuzzy logic development tool is available in two versions - a low cost introductory version, mp explorer, for designers to gain a comprehensive working knowledge of fuzzy logic system design; and a full-featured version, fuzzy tech-mp, edition for implementing more complex systems. both versions include microchips fuzzy lab demonstration board for hands-on experience with fuzzy logic systems implementation. 9.12 de velopment systems for convenience, the development tools are packaged into comprehensive systems as listed in table 9-2. table 9-2: development system packages item name system description 1. picmaster system picmaster in-circuit emulator, pro mate programmer, assembler, soft- ware simulator, samples and your choice of target probe. 2. picstart system picstart low-cost prototype programmer, assembler, software simulator and samples. 3. pro mate system pro mate universal programmer, full featured stand-alone or pc-hosted programmer, assembler, simulator
pic16c5x ds30015m-page 56 1995 microchip technology inc. notes:
1995 microchip technology inc. ds30015m-page 57 pic16c54/55/56/57 pic16c5x 10.0 electrical characteristics - pic16c54/55/56/57 absolute maximum ratings? ambient temperature under bias ........................................................................................................... ?5 c to +125 c storage temperature ............................................................................................................................. ?5 c to +150 c voltage on v dd with respect to v ss ............................................................................................................... 0v to +7.5v voltage on mclr with respect to v ss (2) ......................................................................................................... 0v to +14v voltage on all other pins with respect to v ss ................................................................................. ?.6v to (v dd + 0.6v) total power dissipation (1) ....................................................................................................................................800 mw max. current out of v ss pin ..................................................................................................................................150 ma max. current into v dd pin .......................................................................................................................................50 ma max. current into an input pin (t0cki only) .................................................................................................................... 500 m a input clamp current, i ik (vi < 0 or vi > v dd ) .................................................................................................................... 20 ma output clamp current, i ok (v0 < 0 or v0 > v dd ) ............................................................................................................. 20 ma max. output current sunk by any i/o pin................................................................................................................25 ma max. output current sourced by any i/o pin...........................................................................................................20 ma max. output current sourced by a single i/o port (porta, b or c).......................................................................40 ma max. output current sunk by a single i/o port (porta, b or c) ............................................................................50 ma note 1: power dissipation is calculated as follows: pdis = v dd x {i dd ? i oh } + {(v dd ?v oh ) x i oh } + (v ol x i ol ) note 2: voltage spikes below v ss at the mclr pin, inducing currents greater than 80 ma, may cause latch-up. thus, a series resistor of 50 to 100 w should be used when applying a ?ow?level to the mclr pin rather than pulling this pin directly to v ss ? notice: stresses above those listed under ?aximum ratings?may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this speci?ation is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. this document was created with framemake r404
pic16c5x pic16c54/55/56/57 ds30015m-page 58 1995 microchip technology inc. table 10-1: cross reference of device specs for oscillator configurations (rc, xt & 10) and frequencies of operation (commercial devices) table 10-2: cross reference of device specs for oscillator configurations (hs, lp & jw) and frequencies of operation (commercial devices) osc pic16c5x-rc pic16c5x-xt pic16c5x-10 rc v dd : 3.0 v to 6.2 v i dd : 3.3 ma max. at 5. v i pd : 9 m a max. at 3.0 v, wdt dis freq: 4 mhz max. n/a n/a xt v dd : 3.0v to 6.25v i dd : 1.8 ma typ. at 5.5v i pd : 0.6 m a typ. at 3.0v wdt dis freq: 4 mhz max. v dd : 3.0v to 6.25v i dd : 3.3 ma max. at 5.5v i pd : 9 m a max. at 3.0v, wdt dis freq: 4 mhz max. n/a hs v dd : 4.5v to 5.5v i dd : 9.0 ma typ. at 5.5v i pd : 0.6 m a typ. at 3.0v wdt dis freq: 20 mhz max. n/a v dd : 4.5v to 5.5v i dd : 10 ma max. at 5.5v i pd : 9 m a max. at 3.0v, wdt dis freq: 10 mhz max. lp v dd : 2.5v to 6.25v i dd : 15 m a typ. at 3.0v i pd : 0.6 m a typ. at 3.0v, wdt dis freq: 40 khz max. v dd : 2.5v to 6.25v i dd : 15 m a typ. at 3.0v i pd : 0.6 m a typ. at 3.0v, wdt dis freq: 40 khz max. v dd : 2.5v to 6.25v i dd : 15 m a typ. at 3.0v i pd : 0.6 m a typ. at 3.0v, wdt dis freq: 40 khz max. the shaded sections indicate oscillator selections which should work by design, but are not tested. it is recommended that the user select the device type from information in unshaded sections. osc pic16c5x-hs pic16c5x-lp pic16c5x/jw rc n/a n/a v dd : 3.0v to 6.25v i dd : 3.3 ma max. at 5.5v i pd : 9 m a max. at 3.0v, wdt dis freq: 4 mhz max. xt n/a n/a v dd : 3.0v to 6.25v i dd : 3.3 ma max. at 5.5v i pd : 9 m a max. at 3.0v, wdt dis freq: 4 mhz max. hs v dd : 4.5v to 5.5v i dd : 20 ma max. at 5.5v i pd : 9 m a max. at 3.0v, wdt dis freq: 20 mhz max. n/a v dd : 4.5v to 5.5v i dd : 20 ma max. at 5.5v i pd : 9 m a max. at 3.0v, wdt dis freq: 20 mhz max. lp v dd : 2.5v to 6.25v i dd : 15 m a typ. at 3.0v i pd : 0.6 m a typ. at 3.0v, wdt dis freq: 40 khz max. v dd : 2.5v to 6.25v i dd : 32 m a max. at 32 khz, 3.0v i pd : 9 m a max. at 3.0v, wdt dis freq: 40 khz max. v dd : 2.5v to 6.25v i dd : 32 m a max. at 32 khz, 3.0v i pd : 9 m a max. at 3.0v, wdt dis freq: 40 khz max. the shaded sections indicate oscillator selections which should work by design, but are not tested. it is recommended that the user select the device type from information in unshaded sections.
1995 microchip technology inc. ds30015m-page 59 pic16c54/55/56/57 pic16c5x 10.1 dc characteristics: p ic16c5x-rc, xt , 10, hs, lp (commer cial ) dc characteristics power supply pins standard operating conditions (unless otherwise speci?d) operating temperature 0 c t a +70 c characteristic sym min typ (1) max units conditions supply voltage pic16c5x-rc pic16c5x-xt pic16c5x-10 pic16c5x-hs pic16c5x-lp v dd 3.0 3.0 4.5 4.5 2.5 6.25 6.25 5.5 5.5 6.25 v v v v v f osc = dc to 4 mhz f osc = dc to 4 mhz f osc = dc to 10 mhz f osc = dc to 20 mhz f osc = dc to 40 khz ram data retention voltage (2) v dr 1.5* v device in sleep mode v dd start voltage to ensure power-on reset v por v ss v see section 7.4 for details on power-on reset v dd rise rate to ensure power-on reset s vdd 0.05* v/ms see section 7.4 for details on power-on reset supply current (3) pic16c5x-rc (4) pic16c5x-xt pic16c5x-10 pic16c5x-hs pic16c5x-lp i dd 1.8 1.8 4.8 4.8 9.0 15 3.3 3.3 10 10 20 32 ma ma ma ma ma m a f osc = 4 mhz, v dd = 5.5v f osc = 4 mhz, v dd = 5.5v f osc = 10 mhz, v dd = 5.5v f osc = 10 mhz, v dd = 5.5v f osc = 20 mhz, v dd = 5.5v f osc = 32 khz, v dd = 3.0v, wdt disabled power down current (5) i pd 4.0 0.6 12 9 m a m a v dd = 3.0v, wdt enabled v dd = 3.0v, wdt disabled * these parameters are characterized but not tested. note 1: data in the typical (?yp? column is based on characterization results at 25 c. this data is for design guidance only and is not tested. 2: this is the limit to which v dd can be lowered in sleep mode without losing ram data. 3: the supply current is mainly a function of the operating voltage and frequency. other factors such as bus loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an impact on the current consumption. a) the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tristated, pulled to v ss , t0cki = v dd , mclr = v dd ; wdt enabled/disabled as speci?d. b) for standby current measurements, the conditions are the same, except that the device is in sleep mode. 4: does not include current through rext. the current through the resistor can be estimated by the formula: i r = v dd /2rext (ma) with rext in k w . 5: the power down current in sleep mode does not depend on the oscillator type. power down current is measured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd and v ss .
pic16c5x pic16c54/55/56/57 ds30015m-page 60 1995 microchip technology inc. 10.2 dc characteristics: p ic16c5xi-rc, xt , 10, hs, lp (industrial ) dc characteristics power supply pins standard operating conditions (unless otherwise speci?d) operating temperature ?0 c t a +85 c characteristic sym min typ (1) max units conditions supply voltage pic16c5xi-rc pic16c5xi-xt pic16c5xi-10 pic16c5xi-hs pic16c5xi-lp v dd 3.0 3.0 4.5 4.5 2.5 6.25 6.25 5.5 5.5 6.25 v v v v v f osc = dc to 4 mhz f osc = dc to 4 mhz f osc = dc to 10 mhz f osc = dc to 20 mhz f osc = dc to 40 khz ram data retention voltage (2) v dr 1.5* v device in sleep mode v dd start voltage to ensure power-on reset v por v ss v see section 7.4 for details on power-on reset v dd rise rate to ensure power-on reset s vdd 0.05* v/ms see section 7.4 for details on power-on reset supply current (3) pic16c5xi-rc (4) pic16c5xi-xt pic16c5xi-10 pic16c5xi-hs pic16c5xi-lp i dd 1.8 1.8 4.8 4.8 9.0 19 3.3 3.3 10 10 20 40 ma ma ma ma ma m a f osc = 4 mhz, v dd = 5.5v f osc = 4 mhz, v dd = 5.5v f osc = 10 mhz, v dd = 5.5v f osc = 10 mhz, v dd = 5.5v f osc = 20 mhz, v dd = 5.5v f osc = 32 khz, vdd = 3.0v, wdt disabled power down current (5) i pd 5.0 0.6 14 12 m a m a v dd = 3.0v, wdt enabled v dd = 3.0v, wdt disabled * these parameters are characterized but not tested. note 1: data in the typical (?yp? column is based on characterization results at 25 c. this data is for design guidance only and is not tested. 2: this is the limit to which v dd can be lowered in sleep mode without losing ram data. 3: the supply current is mainly a function of the operating voltage and frequency. other factors such as bus loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an impact on the current consumption. a) the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tristated, pulled to v ss , t0cki = v dd , mclr = v dd ; wdt enabled/disabled as speci?d. b) for standby current measurements, the conditions are the same, except that the device is in sleep mode. 4: does not include current through rext. the current through the resistor can be estimated by the formula: i r = v dd /2rext (ma) with rext in k w . 5: the power down current in sleep mode does not depend on the oscillator type. power down current is measured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd and v ss .
1995 microchip technology inc. ds30015m-page 61 pic16c54/55/56/57 pic16c5x 10.3 dc characteristics: pic16c5xe-rc, xt , 10, hs, lp (a utomotive) dc characteristics power supply pins standard operating conditions (unless otherwise speci?d) operating temperature ?0 c t a +125 c characteristic sym min typ (1) max units conditions supply voltage pic16c5xe-rc pic16c5xe-xt pic16c5xe-10 pic16c5xe-hs pic16c5xe-lp v dd 3.25 3.25 4.5 4.5 2.5 6.0 6.0 5.5 5.5 6.0 v v v v v f osc = dc to 4 mhz f osc = dc to 4 mhz f osc = dc to 10 mhz f osc = dc to 16 mhz f osc = dc to 40 khz ram data retention voltage (2) v dr 1.5* v device in sleep mode v dd start voltage to ensure power-on reset v por v ss v see section 7.4 for details on power-on reset v dd rise rate to ensure power-on reset s vdd 0.05* v/ms see section 7.4 for details on power-on reset supply current (3) pic16c5xe-rc (4) pic16c5xe-xt pic16c5xe-10 pic16c5xe-hs pic16c5xe-lp i dd 1.8 1.8 4.8 4.8 9.0 25 3.3 3.3 10 10 20 55 ma ma ma ma ma m a f osc = 4 mhz, v dd = 5.5v f osc = 4 mhz, v dd = 5.5v f osc = 10 mhz, v dd = 5.5v f osc = 10 mhz, v dd = 5.5v f osc = 16 mhz, v dd = 5.5v f osc = 32 khz, v dd = 3.25v, wdt disabled power down current (5) i pd 5.0 0.8 22 18 m a m a v dd = 3.25v, wdt enabled v dd = 3.25v, wdt disabled * these parameters are characterized but not tested. note 1: data in the typical (?yp? column is based on characterization results at 25 c. this data is for design guidance only and is not tested. 2: this is the limit to which v dd can be lowered in sleep mode without losing ram data. 3: the supply current is mainly a function of the operating voltage and frequency. other factors such as bus loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an impact on the current consumption. a) the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tristated, pulled to v ss , t0cki = v dd , mclr = v dd ; wdt enabled/disabled as speci?d. b) for standby current measurements, the conditions are the same, except that the device is in sleep mode. 4: does not include current through rext. the current through the resistor can be estimated by the formula: i r = v dd /2rext (ma) with rext in k w . 5: the power down current in sleep mode does not depend on the oscillator type. power down current is measured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd and v ss .
pic16c5x pic16c54/55/56/57 ds30015m-page 62 1995 microchip technology inc. 10.4 dc characteristics: p ic16c5x-rc, xt , 10, hs, lp (commer cial) pic16c5xi-rc, xt , 10, hs, lp (industrial) dc characteristics all pins except power supply pins standard operating conditions (unless otherwise speci?d) operating temperature 0 c t a +70 c (commercial) ?0 c t a +85 c (industrial) operating voltage v dd range is described in section 10.1, section 10.2 and section 10.3. characteristic sym min typ (1) max units conditions input low voltage i/o ports mclr (schmitt trigger) t0cki (schmitt trigger) osc1 (schmitt trigger) v il v ss v ss v ss v ss v ss 0.2 v dd 0.15 v dd 0.15 v dd 0.15 v dd 0.3 v dd v v v v v pin at hi-impedance pic16c5x-rc only (4) pic16c5x-xt, 10, hs, lp input high voltage i/o ports mclr (schmitt trigger) t0cki (schmitt trigger) osc1 (schmitt trigger) v ih 0.45 v dd 2.0 0.36 v dd 0.85 v dd 0.85 v dd 0.85 v dd 0.7 v dd v dd v dd v dd v dd v dd v dd v dd v v v v v v v for all v dd (5) 4.0v < v dd 5.5v (5) v dd > 5.5v pic16c5x-rc only (4) pic16c5x-xt, 10, hs, lp hysteresis of schmitt trigger inputs v hys 0.15v dd *v input leakage current (2,3) i/o ports mclr t0cki osc1 i il ? ? ? ? 0.5 0.5 0.5 0.5 +1 +5 +3 +3 m a m a m a m a m a for v dd 5.5v v ss v pin v dd , pin at hi-impedance v pin = v ss + 0.25v v pin = v dd v ss v pin v dd v ss v pin v dd , pic16c5x-xt, 10, hs, lp output low voltage i/o ports osc2/clkout v ol 0.6 0.6 v v i ol = 8.7 ma, v dd = 4.5v i ol = 1.6 ma, v dd = 4.5v, pic16c5x-rc output high voltage i/o ports (3) osc2/clkout v oh v dd ?0.7 v dd ?0.7 v v i oh = ?.4 ma, v dd = 4.5v i oh = ?.0 ma, v dd = 4.5v, pic16c5x-rc * these parameters are characterized but not tested. note 1: data in the typical (?yp? column is based on characterization results at 25 c. this data is for design guidance only and is not tested. 2: the leakage current on the mclr /v pp pin is strongly dependent on the applied voltage level. the speci?d levels represent normal operating conditions. higher leakage current may be measured at different input voltage. 3: negative current is de?ed as coming out of the pin. 4: for pic16c5x-rc devices, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the pic16c5x be driven with external clock in rc mode. 5: the user may use the better of the two speci?ations.
1995 microchip technology inc. ds30015m-page 63 pic16c54/55/56/57 pic16c5x 10.5 dc characteristics: pic16c5x-rc, xt , 10, hs, lp (a utomotive) dc characteristics all pins except power supply pins standard operating conditions (unless otherwise speci?d) operating temperature ?0 c t a +125 c operating voltage v dd range is described in section 10.1, section 10.2 and section 10.3. characteristic sym min typ (1) max units conditions input low voltage i/o ports mclr (schmitt trigger) t0cki (schmitt trigger) osc1 (schmitt trigger) v il vss vss vss vss vss 0.15 v dd 0.15 v dd 0.15 v dd 0.15 v dd 0.3 v dd v v v v v pin at hi-impedance pic16c5x-rc only (4) pic16c5x-xt, 10, hs, lp input high voltage i/o ports mclr (schmitt trigger) t0cki (schmitt trigger) osc1 (schmitt trigger) v ih 0.45 v dd 2.0 0.36 v dd 0.85 v dd 0.85 v dd 0.85 v dd 0.7 v dd v dd v dd v dd v dd v dd v dd v dd v v v v v v v for all v dd (5) 4.0v < v dd 5.5v (5) v dd > 5.5 v pic16c5x-rc only (4) pic16c5x-xt, 10, hs, lp hysteresis of schmitt trigger inputs v hys 0.15v dd *v input leakage current (2,3) i/o ports mclr t0cki osc1 i il ? ? ? ? 0.5 0.5 0.5 0.5 +1 +5 +3 +3 m a m a m a m a m a for v dd 5.5 v v ss v pin v dd , pin at hi-impedance v pin = v ss + 0.25v v pin = v dd v ss v pin v dd v ss v pin v dd , pic16c5x-xt, 10, hs, lp output low voltage i/o ports osc2/clkout v ol 0.6 0.6 v v i ol = 8.7 ma, v dd = 4.5v i ol = 1.6 ma, v dd = 4.5v, pic16c5x-rc output high voltage i/o ports (3) osc2/clkout v oh v dd ?0.7 v dd ?0.7 v v i oh = ?.4 ma, v dd = 4.5v i oh = ?.0 ma, v dd = 4.5v, pic16c5x-rc * these parameters are characterized but not tested. note 1: data in the typical (?yp? column is based on characterization results at 25 c. this data is for design guidance only and is not tested. 2: the leakage current on the mclr /v pp pin is strongly dependent on the applied voltage level. the speci?d levels represent normal operating conditions. higher leakage current may be measured at different input voltage. 3: negative current is de?ed as coming out of the pin. 4: for pic16c5x-rc devices, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the pic16c5x be driven with external clock in rc mode. 5: the user may use the better of the two speci?ations.
pic16c5x pic16c54/55/56/57 ds30015m-page 64 1995 microchip technology inc. 10.6 t iming p arameter symbology a nd load conditions the timing parameter symbols have been created following one of the following formats: 1. tpps2pps 2. tpps t f frequency t time lowercase subscripts (pp) and their meanings: pp 2 to mc mclr ck clkout osc oscillator cy cycle time os osc1 drt device reset timer t0 t0cki io i/o port wdt watchdog timer uppercase letters and their meanings: s f fall p period h high r rise i invalid (hi-impedance) v valid l low z hi-impedance figure 10-1: load conditions - pic16c54/55/56/57 c l v ss pin c l = 50 pf for all pins except osc2 15 pf for osc2 in xt, hs or lp modes when external clock is used to drive osc1
1995 microchip technology inc. ds30015m-page 65 pic16c54/55/56/57 pic16c5x 10.7 timing dia grams and speci cations figure 10-2: external clock timing - pic16c54/55/56/57 table 10-3: external clock timing requirements - pic16c54/55/56/57 ac characteristics standard operating conditions (unless otherwise speci?d) operating temperature 0 c t a +70 c (commercial), ?0 c t a +85 c (industrial), ?0 c t a +125 c (automotive) operating voltage v dd range is described in section 10.1, section 10.2 and section 10.3 parameter no. sym characteristic min typ (1) max units conditions f osc external clkin frequency (2) dc 4 mhz rc osc mode dc 4 mhz xt osc mode dc 10 mhz 10 mhz mode dc 20 mhz hs osc mode (com/indust) dc 16 mhz hs osc mode (automotive) dc 40 khz lp osc mode oscillator frequency (2) dc 4 mhz rc osc mode 0.1 4 mhz xt osc mode 4 10 mhz 10 mhz mode 4 20 mhz hs osc mode (com/indust) 4 16 mhz hs osc mode (automotive) dc 40 khz lp osc mode * these parameters are characterized but not tested. note 1: data in the typical (?yp? column is at 5.0v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. 2: all speci?d values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. exceeding these speci?d limits may result in an unstable oscillator operation and/or higher than expected current consumption. when an external clock input is used, the ?ax?cycle time limit is ?c?(no clock) for all devices. 3: instruction cycle period (t cy ) equals four times the input oscillator time base period. osc1 clkout q4 q1 q2 q3 q4 q1 133 44 2
pic16c5x pic16c54/55/56/57 ds30015m-page 66 1995 microchip technology inc. 1t osc external clkin period (2) 250 ns rc osc mode 250 ns xt osc mode 100 ns 10 mhz mode 50 ns hs osc mode (com/indust) 62.5 ns hs osc mode (automotive) 25 m s lp osc mode oscillator period (2) 250 ns rc osc mode 250 10,000 ns xt osc mode 100 250 ns 10 mhz mode 50 250 ns hs osc mode (com/indust) 62.5 250 ns hs osc mode (automotive) 25 m s lp osc mode 2t cy instruction cycle time (3) 4/f osc 3 tosl, tosh clock in (osc1) low or high time 50* ns xt oscillator 20* ns hs oscillator 2* m s lp oscillator 4 tosr, tosf clock in (osc1) rise or fall time 25* ns xt oscillator 25* ns hs oscillator 50* ns lp oscillator table 10-3: external clock timing requirements - pic16c54/55/56/57 (con?) ac characteristics standard operating conditions (unless otherwise speci?d) operating temperature 0 c t a +70 c (commercial), ?0 c t a +85 c (industrial), ?0 c t a +125 c (automotive) operating voltage v dd range is described in section 10.1, section 10.2 and section 10.3 parameter no. sym characteristic min typ (1) max units conditions * these parameters are characterized but not tested. note 1: data in the typical (?yp? column is at 5.0v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. 2: all speci?d values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. exceeding these speci?d limits may result in an unstable oscillator operation and/or higher than expected current consumption. when an external clock input is used, the ?ax?cycle time limit is ?c?(no clock) for all devices. 3: instruction cycle period (t cy ) equals four times the input oscillator time base period.
1995 microchip technology inc. ds30015m-page 67 pic16c54/55/56/57 pic16c5x figure 10-3: clkout and i/o timing - pic16c54/55/56/57 table 10-4: clkout and i/o timing requirements - pic16c54/55/56/57 ac characteristics standard operating conditions (unless otherwise speci?d) operating temperature 0 c t a +70 c (commercial), ?0 c t a +85 c (industrial), ?0 c t a +125 c (automotive) operating voltage v dd range is described in section 10.1, section 10.2 and section 10.3 parameter no. sym characteristic min typ (1) max units 10 tosh2ckl osc1 to clkout (2) 15 30** ns 11 tosh2ckh osc1 to clkout (2) 15 30** ns 12 tckr clkout rise time (2) 5 15** ns 13 tckf clkout fall time (2) 5 15** ns 14 tckl2iov clkout to port out valid (2) 40** ns 15 tiov2ckh port in valid before clkout (2) 0.25 t cy + 30* ns 16 tckh2ioi port in hold after clkout (2) 0* ns 17 tosh2iov osc1 (q1 cycle) to port out valid (3) 100* ns 18 tosh2ioi osc1 (q2 cycle) to port input invalid (i/o in hold time) tbd ns 19 tiov2osh port input valid to osc1 (i/o in setup time) tbd ns 20 tior port output rise time (3) 10 25** ns 21 tiof port output fall time (3) 10 25** ns * these parameters are characterized but not tested. ** these parameters are design targets and are not tested. no characterization data available at this time. note 1: data in the typical (?yp? column is at 5.0v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. 2: measurements are taken in rc mode where clkout output is 4 x t osc . 3: see figure 10-1 for loading conditions. osc1 clkout i/o pin (input) i/o pin (output) q4 q1 q2 q3 10 13 14 17 20, 21 18 15 11 12 16 old value new value note: all tests must be done with speci?d capacitive loads (see data sheet) 50 pf on i/o pins and clkout. 19
pic16c5x pic16c54/55/56/57 ds30015m-page 68 1995 microchip technology inc. figure 10-4: reset, watchdog timer, and device reset timer timing - pic16c54/55/56/57 table 10-5: reset, watchdog timer, and device reset timer - pic16c54/55/56/57 ac characteristics standard operating conditions (unless otherwise speci?d) operating temperature 0 c t a +70 c (commercial), ?0 c t a +85 c (industrial), ?0 c t a +125 c (automotive) operating voltage v dd range is described in section 10.1, section 10.2 and section 10.3 parameter no. sym characteristic min typ (1) max units conditions 30 tmcl mclr pulse width (low) 100* ns v dd = 5.0v 31 twdt watchdog timer time-out period (no prescaler) 9* 18* 30* ms v dd = 5.0v (commercial) 32 t drt device reset timer period 9* 18* 30* ms v dd = 5.0v (commercial) 34 tio z i/o hi-impedance from mclr low 100* ns * these parameters are characterized but not tested. note 1: data in the typical (?yp? column is at 5.0v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. v dd mclr internal por drt time-out internal reset watchdog timer reset 32 31 34 i/o pin 32 32 34 (note 1) note 1: i/o pins must be taken out of hi-impedance mode by enabling the output drivers in software. 30
1995 microchip technology inc. ds30015m-page 69 pic16c54/55/56/57 pic16c5x figure 10-5: timer0 clock timings - pic16c54/55/56/57 table 10-6: timer0 clock requirements - pic16c54/55/56/57 ac characteristics standard operating conditions (unless otherwise speci?d) operating temperature 0 c t a +70 c (commercial), ?0 c t a +85 c (industrial), ?0 c t a +125 c (automotive) operating voltage v dd range is described in section 10.1, section 10.2 and section 10.3 parameter no. sym characteristic min typ (1) max units conditions 40 tt0h t0cki high pulse width - no prescaler 0.5 t cy + 20* ns - with prescaler 10* ns 41 tt0l t0cki low pulse width - no prescaler 0.5 t cy + 20* ns - with prescaler 10* ns 42 tt0p t0cki period 20 or t cy + 40 * n ns whichever is greater. n = prescale value (1, 2, 4,..., 256) * these parameters are characterized but not tested. note 1: data in the typical (?yp? column is at 5.0v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. t0cki 40 41 42
pic16c5x pic16c54/55/56/57 ds30015m-page 70 1995 microchip technology inc. notes:
1995 microchip technology inc. ds30015m-page 71 pic16c54/55/56/57 pic16c5x 11.0 dc and ac characteristics - pic16c54/55/56/57 the graphs and tables provided in this section are for design guidance and are not tested or guaranteed. in some graphs or tables the data presented are outside speci?d operating range (e.g., outside speci?d v dd range). this is for information only and devices will operate properly only within the speci?d range. the data presented in this section is a statistical summary of data collected on units from different lots over a period of time. ?ypical?represents the mean of the distribution while ?ax?or ?in?represents (mean + 3 s ) and (mean ?3 s ) respectively, where s is standard deviation. figure 11-1: typical rc oscillator frequency vs. temperature table 11-1: rc oscillator frequencies cext rext average fosc @ 5 v, 25 c 20 pf 3.3 k 4.973 mhz 27% 5 k 3.82 mhz 21% 10 k 2.22 mhz 21% 100 k 262.15 khz 31% 100 pf 3.3 k 1.63 mhz 13% 5 k 1.19 mhz 13% 10 k 684.64 khz 18% 100 k 71.56 khz 25% 300 pf 3.3 k 660 khz 10% 5.0 k 484.1 khz 14% 10 k 267.63 khz 15% 160 k 29.44 khz 19% the frequencies are measured on dip packages. the percentage variation indicated here is part-to-part variation due to normal process distribution. the variation indicated is 3 standard deviation from average value for v dd = 5 v. f osc f osc (25 c) 1.10 1.08 1.06 1.04 1.02 1.00 0.98 0.96 0.94 0.92 0.90 010 20253040506070 t( c) frequency normalized to +25 c v dd = 5.5 v v dd = 3.5 v rext 10 k w cext = 100 pf 0.88 this document was created with framemake r404
pic16c5x pic16c54/55/56/57 ds30015m-page 72 1995 microchip technology inc. figure 11-2: typical rc oscillator frequency vs. v dd , c ext = 20 p f 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd (volts) f osc (mhz) r = 3.3k r = 5k r = 10k r = 100k measured on dip packages, t = 25 c figure 11-3: typical rc oscillator frequency vs. v dd , c ext = 100 p f figure 11-4: typical rc oscillator frequency vs. v dd , c ext = 300 p f 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd (volts) f osc (mhz) r = 3.3k r = 5k r = 10k r = 100k measured on dip packages, t = 25 c 800 700 600 500 400 300 200 100 0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd (volts) f osc (khz) r = 3.3k r = 5k r = 10k r = 100k measured on dip packages, t = 25 c
1995 microchip technology inc. ds30015m-page 73 pic16c54/55/56/57 pic16c5x figure 11-5: typical i pd vs. v dd , watchdog disabled figure 11-6: maximum i pd vs. v dd , watchdog disabled 2.5 2.0 1.5 1.0 0.5 0.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i pd ( m a) v dd (volts) t = 25 c 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i pd (ma) v dd (volts) 1 6.5 7.0 10 100 +85?c 0?c ?0?c ?5?c +125?c +70?c figure 11-7: typical i pd vs. v dd , watchdog enabled figure 11-8: maximum i pd vs. v dd , watchdog enabled 20 16 12 8 4 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i pd ( m a) v dd (volts) 2 6 10 14 18 t = 25 c +70 c 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i pd ( m a) v dd (volts) 6.5 7.0 40 60 +85 c ?0 c ?5 c 10 20 30 50 i pd , with wdt enabled, has two components: the leakage current which increases with higher temperature and the operating current of the wdt logic which increases with lower temperature. at ?0 c, the latter dominates explaining the apparently anomalous behavior. +125 c 0 c
pic16c5x pic16c54/55/56/57 ds30015m-page 74 1995 microchip technology inc. figure 11-9: v th (input threshold voltage) of i/o pins vs. v dd figure 11-10: v ih , v il of mclr , t0cki and osc1 (in rc mode) vs. v dd figure 11-11: v th (input threshold voltage) of osc1 input (in xt, hs, and lp modes) vs. v dd 2.00 1.80 1.60 1.40 1.20 1.00 2.5 3.0 3.5 4.0 4.5 5.0 v dd (volts) min (?0 c to +85 c) 0.80 0.60 5.5 6.0 max (?0 c to +85 c) typ (+25 c) v th (volts) 3.5 3.0 2.5 2.0 1.5 1.0 2.5 3.0 3.5 4.0 4.5 5.0 v dd (volts) 0.5 0.0 5.5 6.0 v ih , v il (volts) 4.0 4.5 v ih min (?0 c to +85 c) v ih max (?0 c to +85 c) v ih typ +25 c v il min ( ?0 c to +85 c) v il max (?0 c to +85 c) v ih typ +25 c note: these input pins have schmitt trigger input buffers. 2.4 2.2 2.0 1.8 1.6 1.4 2.5 3.0 3.5 4.0 4.5 5.0 v dd (volts) 1.2 1.0 5.5 6.0 typ (+25 c) v th (volts) 2.6 2.8 3.0 3.2 3.4 max (?0 c to +85 c) min (?0 c to +85 c)
1995 microchip technology inc. ds30015m-page 75 pic16c54/55/56/57 pic16c5x figure 11-12: typical i dd vs. frequency (external clock, 25 c) figure 11-13: maximum i dd vs. frequency (external clock, ?0 c to +85 c) 10k 100k 1m 10m 100m 0.01 0.1 1.0 10 i dd (ma) external clock frequency (hz) 5.0 4.5 4.0 2.5 3.0 3.5 5.5 6.0 6.5 7.0 10k 100k 1m 10m 100m 0.01 0.1 1.0 10 i dd (ma) external clock frequency (hz) 5.0 4.5 4.0 3.5 5.5 6.0 6.5 7.0 2.5 3.0
pic16c5x pic16c54/55/56/57 ds30015m-page 76 1995 microchip technology inc. figure 11-14: maximum i dd vs. frequency (external clock ?5 c to +125 c) 10k 100k 1m 10m 100m 0.01 0.1 1.0 10 i dd (ma) external clock frequency (hz) 5.0 4.5 4.0 2.5 3.0 3.5 5.5 6.0 6.5 7.0 figure 11-15: wdt timer time-out period vs. v dd 50 45 40 35 30 25 20 15 10 5 234567 v dd (volts) wdt period (ms) max +85 c max +70 c typ +25 c min 0 c min ?0 c figure 11-16: transconductance (gm) of hs oscillator vs. v dd 9000 8000 7000 6000 5000 4000 3000 2000 100 0 234567 v dd (volts) gm ( m a/v) min +85 c max ?0 c typ +25 c
1995 microchip technology inc. ds30015m-page 77 pic16c54/55/56/57 pic16c5x figure 11-17: transconductance (gm) of lp oscillator vs. v dd figure 11-18: i oh vs. v oh , v dd = 3 v 45 40 35 30 25 20 15 10 5 0 234567 v dd (volts) gm ( m a/v) min +85 c max ?0 c typ +25 c 0 ? ?0 ?5 ?0 ?5 0 0.5 1.0 1.5 2.0 2.5 v oh (volts) i oh (ma) min +85 c 3.0 typ +25 c max ?0 c figure 11-19: transconductance (gm) of xt oscillator vs. v dd figure 11-20: i oh vs. v oh , v dd = 5 v 2500 2000 1500 1000 500 0 234567 v dd (volts) gm ( m a/v) min +85 c max ?0 c typ +25 c 0 ?0 ?0 ?0 ?0 1.5 2.0 2.5 3.0 3.5 4.0 v oh (volts) i oh (ma) min +85 c max ?0 c 4.5 5.0 typ +25 c
pic16c5x pic16c54/55/56/57 ds30015m-page 78 1995 microchip technology inc. figure 11-21: i ol vs. v ol , v dd = 3 v table 11-2: input capacitance for pic16c54/56 pin typical capacitance (pf) 18l pdip 18l soic ra port 5.0 4.3 rb port 5.0 4.3 mclr 17.0 17.0 osc1 4.0 3.5 osc2/clkout 4.3 3.5 t0cki 3.2 2.8 all capacitance values are typical at 25 c. a part-to-part variation of 25% (three standard deviations) should be taken into account. 45 40 35 30 25 20 15 10 5 0 0.0 0.5 1.0 1.5 2.0 2.5 v ol (volts) i ol (ma) min +85 c max ?0 c typ +25 c 3.0 figure 11-22: i ol vs. v ol , v dd = 5 v table 11-3: input capacitance for pic16c55/57 pin typical capacitance (pf) 28l pdip (600 mil) 28l soic ra port 5.2 4.8 rb port 5.6 4.7 rc port 5.0 4.1 mclr 17.0 17.0 osc1 6.6 3.5 osc2/clkout 4.6 3.5 t0cki 4.5 3.5 all capacitance values are typical at 25 c. a part-to-part variation of 25% (three standard deviations) should be taken into account. 90 80 70 60 50 40 30 20 10 0 0.0 0.5 1.0 1.5 2.0 2.5 v ol (volts) i ol (ma) min +85 c max ?0 c typ +25 c 3.0
1995 microchip technology inc. ds30015m-page 79 pic16cr54 pic16c5x not recommended for new designs 12.0 electrical characteristics - pic16cr54 absolute maximum ratings? ambient temperature under bias ........................................................................................................... ?5 c to +125 c storage temperature ............................................................................................................................. ?5 c to +150 c voltage on v dd with respect to v ss ..................................................................................................................0 to +7.5v voltage on mclr with respect to v ss (2) .........................................................................................................0 to +14.0v voltage on all other pins with respect to v ss ................................................................................ ?.6 v to (v dd + 0.6v) total power dissipation (1) ....................................................................................................................................800 mw max. current out of v ss pin ..................................................................................................................................150 ma max. current into v dd pin .......................................................................................................................................50 ma max. current into an input pin (t0cki only) .................................................................................................................... 500 m a input clamp current, i ik (vi < 0 or vi > v dd ) .................................................................................................................... 20 ma output clamp current, i ok (v0 < 0 or v0 > v dd ) ............................................................................................................. 20 ma max. output current sunk by any i/o pin................................................................................................................25 ma max. output current sourced by any i/o pin...........................................................................................................20 ma max. output current sourced by a single i/o port (porta or b)............................................................................40 ma max. output current sunk by a single i/o port (porta or b).................................................................................50 ma note 1: power dissipation is calculated as follows: p dis = v dd x {i dd - i oh } + {(v dd -v oh ) x i oh } + (v ol x i ol ) note 2: voltage spikes below vss at the mclr pin, inducing currents greater than 80 ma may cause latch-up. thus, a series resistor of 50 to 100 w should be used when applying a low level to the mclr pin rather than pulling this pin directly to vss. ? notice: stresses above those listed under "maximum ratings" may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this speci?ation is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. not recommended for new designs this document was created with framemake r404
pic16c5x pic16cr54 ds30015m-page 80 1995 microchip technology inc. not recommended for new designs table 12-1: cross reference of device specs for oscillator configurations and frequencies of operation (commercial devices) osc pic16cr54-rc pic16cr54-xt pic16cr54-10 pic16cr54-hs pic16cr54-lp rc v dd : 2.5v to 6.25v i dd : 3.6 ma max at 6.0v i pd : 6 m a max at 2.5v, wdt dis freq: 4 mhz max n/a n/a n/a n/a xt n/a v dd : 2.5v to 6.25v i dd : 3.6 ma max at 6.0v i pd : 6 m a max at 2.5v, wdt dis freq: 4 mhz max n/a n/a n/a hs n/a n/a v dd : 4.5v to 5.5v i dd : 10 ma max at 5.5v i pd : 6 m a max at 2.5v, wdt dis freq: 10 mhz max v dd : 4.5v to 5.5v i dd : 20 ma max at 5.5v i pd : 6 m a max at 2.5v, wdt dis freq: 20 mhz max n/a lp n/a n/a n/a n/a v dd : 2.0v to 6.25v i dd : 20 m a max at 32 khz, 2.0v i pd : 6 m a max at 2.5v, wdt dis freq: 200 khz max the shaded sections indicate oscillator selections which should work by design, but are not tested. it is recommended that the user select the device type from information in unshaded sections. not recommended for new designs
1995 microchip technology inc. ds30015m-page 81 pic16cr54 pic16c5x not recommended for new designs 12.1 dc characteristics: pic16cr54-rc, xt , hs, lp (commer cial ) pic16cr54i-rc, xt , hs, lp (industrial) dc characteristics power supply pins standard operating conditions (unless otherwise speci?d) operating temperature 0 c t a +70 c (commercial) ?0 c t a +85 c (industrial) characteristic sym min typ (1) max units conditions supply voltage pic16cr54-rc pic16cr54-xt pic16cr54-10 pic16cr54-hs pic16cr54-lp v dd 2.5 2.5 4.5 4.5 2.0 6.25 6.25 5.5 5.5 6.25 v v v v v f osc = dc to 4 mhz f osc = dc to 4 mhz f osc = dc to 10 mhz f osc = dc to 20 mhz f osc = dc to 200 khz ram data retention voltage (2) v dr 1.5* v device in sleep mode v dd start voltage to ensure power-on reset v por v ss v see section 7.4 for details on power-on reset v dd rise rate to ensure power-on reset s vdd 0.05* v/ms see section 7.4 for details on power-on reset supply current (3) pic16cr54-rc (4) , xt pic16cr54-10 pic16cr54-hs pic16cr54-lp i dd 2.0 0.8 90 4.8 4.8 9.0 10.0 3.6 1.8 350 10 10 20 20 70 ma ma m a ma ma ma m a m a f osc = 4 mhz, v dd = 6.0v f osc = 4 mhz, v dd = 3.0v f osc = 200 khz, v dd = 2.5v f osc = 10 mhz, v dd = 5.5v f osc = 10 mhz, v dd = 5.5v f osc = 20 mhz, v dd = 5.5v f osc = 32 khz, v dd = 2.0v f osc = 32 khz, v dd = 6.0v power-down current commercial (5) i pd 1 2 3 5 6 8* 15 25 m a m a m a m a v dd = 2.5v, wdt disabled v dd = 4.0v, wdt disabled v dd = 6.0v, wdt disabled v dd = 6.0v, wdt enabled power-down current industrial (5) i pd 1 2 3 3 5 8 10* 20* 18 45 m a m a m a m a m a v dd = 2.5v, wdt disabled v dd = 4.0v, wdt disabled v dd = 4.0v, wdt enabled v dd = 6.0v, wdt disabled v dd = 6.0v, wdt enabled * these parameters are characterized but not tested. note 1: data in the typical (?yp? column is based on characterization results at 25 c. this data is for design guidance only and is not tested. 2: this is the limit to which v dd can be lowered in sleep mode without losing ram data. 3: the supply current is mainly a function of the operating voltage and frequency. other factors such as bus loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an impact on the current consumption. a) the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tristated, pulled to v ss , t0cki = v dd , mclr = v dd ; wdt enabled/disabled as speci?d. b) for standby current measurements, the conditions are the same, except that the device is in sleep mode. 4: does not include current through rext. the current through the resistor can be estimated by the formula: i r = v dd /2rext (ma) with rext in k w . 5: the power down current in sleep mode does not depend on the oscillator type. power down current is measured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd and v ss .
pic16c5x pic16cr54 ds30015m-page 82 1995 microchip technology inc. not recommended for new designs 12.2 dc characteristics: pic16cr54e-rc, xt , hs, lp (a utomotive ) dc characteristics power supply pins standard operating conditions (unless otherwise speci?d) operating temperature ?0 c t a +125 c characteristic sym min typ (1) max units conditions supply voltage pic16cr54e-rc pic16cr54e-xt pic16cr54e-10 pic16cr54e-hs pic16cr54e-lp v dd 3.25 3.25 4.5 4.5 2.5 6.0 6.0 5.5 5.5 6.0 v v v v v f osc = dc to 4 mhz f osc = dc to 4 mhz f osc = dc to 10 mhz f osc = dc to 16 mhz f osc = dc to 200 khz ram data retention voltage (2) v dr 1.5* v device in sleep mode v dd start voltage to ensure power-on reset v por v ss v see section 7.4 for details on power-on reset v dd rise rate to ensure power-on reset s vdd 0.05* v/ms see section 7.4 for details on power-on reset supply current (3) pic16cr54e-rc (4) pic16cr54e-xt pic16cr54e-10 pic16cr54e-hs pic16cr54e-lp i dd 1.8 1.8 4.8 4.8 9.0 25 3.3 3.3 10 10 20 55 ma ma ma ma ma m a f osc = 4 mhz, v dd = 5.5v f osc = 4 mhz, v dd = 5.5v f osc = 10 mhz, v dd = 5.5v f osc = 10 mhz, v dd = 5.5v f osc = 16 mhz, v dd = 5.5v f osc = 32 khz, v dd = 3.25v, wdt disabled power-down current (5) i pd 5 0.8 22 18 m a m a v dd = 3.25v, wdt enabled v dd = 3.25v, wdt disabled * these parameters are characterized but not tested. note 1: data in the typical (?yp? column is based on characterization results at 25 c. this data is for design guid- ance only and is not tested. 2: this is the limit to which v dd can be lowered in sleep mode without losing ram data. 3: the supply current is mainly a function of the operating voltage and frequency. other factors such as bus loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an impact on the current consumption. a) the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tristated, pulled to v ss , t0cki = v dd , mclr = v dd ; wdt enabled/disabled as speci?d. b) for standby current measurements, the conditions are the same, except that the device is in sleep mode. 4: does not include current through rext. the current through the resistor can be estimated by the formula: i r = v dd /2rext (ma) with rext in k w . 5: the power down current in sleep mode does not depend on the oscillator type. power down current is measured with the part in sleep mode, with all i/o pins in hi-impedance state and tied to v dd and v ss .
1995 microchip technology inc. ds30015m-page 83 pic16cr54 pic16c5x not recommended for new designs 12.3 dc characteristics: pic16cr54-rc, xt , hs, lp (commer cial) pic16cr54i-rc, xt , hs, lp (industrial) dc characteristics all pins except power supply pins standard operating conditions (unless otherwise speci?d) operating temperature 0 c t a +70 c (commercial) ?0 c t a +85 c (industrial) operating voltage v dd range is described in section 12.1. characteristic sym min typ (1) max units conditions input low voltage i/o ports mclr (schmitt trigger) t0cki (schmitt trigger) osc1 (schmitt trigger) v il v ss v ss v ss v ss v ss 0.20 v dd 0.15 v dd 0.15 v dd 0.15 v dd 0.15 v dd v v v v v pin at hi-impedance pic16cr54-rc only (4) pic16cr54-xt, 10, hs, lp input high voltage i/o ports mclr (schmitt trigger) t0cki (schmitt trigger) osc1 (schmitt trigger) v ih 2.0 0.6 v dd 0.85 v dd 0.85 v dd 0.85 v dd 0.85 v dd v dd v dd v dd v dd v dd v dd v v v v v v v dd = 3.0v to 5.5v (5) full v dd range (5) pic16cr54-rc only (4) pic16cr54-xt, 10, hs, lp hysteresis of schmitt trigger inputs v hys 0.15v dd *v input leakage current (2,3) i/o ports mclr t0cki osc1 i il ? ? ? ? 0.5 0.5 0.5 +1 +5 +5 +3 m a m a m a m a m a for v dd 5.5 v v ss v pin v dd , pin at hi-impedance v pin = v ss + 0.25v v pin = v dd v ss v pin v dd v ss v pin v dd , pic16cr54-xt, 10, hs, lp output low voltage i/o ports osc2/clkout vol 0.5 0.5 v v i ol = 10 ma, v dd = 6.0v i ol = 1.9 ma, v dd = 6.0v output high voltage (3,4) i/o ports osc2/clkout v oh v dd ?.5 v dd ?.5 v v i oh = ?.0 ma, v dd = 6.0v i oh = ?.8 ma, v dd = 6.0v * these parameters are characterized but not tested. note 1: data in the typical (?yp? column is based on characterization results at 25 c. this data is for design guidance only and is not tested. 2: the leakage current on the mclr /v pp pin is strongly dependent on the applied voltage level. the speci?d levels represent normal operating conditions. higher leakage current may be measured at different input voltage. 3: negative current is de?ed as coming out of the pin. 4: for pic16c5x-rc devices, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the pic16c5x be driven with external clock in rc mode. 5: the user may use the better of the two speci?ations.
pic16c5x pic16cr54 ds30015m-page 84 1995 microchip technology inc. not recommended for new designs 12.4 dc characteristics: p ic16cr54e-rc, xt , hs, lp (a utomotive) dc characteristics all pins except power supply pins standard operating conditions (unless otherwise speci?d) operating temperature ?0 c t a +125 c operating voltage v dd range is described in section 12.2. characteristic sym min typ (1) max units conditions input low voltage i/o ports mclr (schmitt trigger) t0cki (schmitt trigger) osc1 (schmitt trigger) v il vss vss vss vss vss 0.15 v dd 0.15 v dd 0.15 v dd 0.15 v dd 0.3 v dd v v v v v pin at hi-impedance pic16cr54e-rc only (4) pic16cr54e-xt, 10, hs, lp input high voltage i/o ports mclr (schmitt trigger) t0cki (schmitt trigger) osc1 (schmitt trigger) v ih 0.45 v dd 2.0 0.36 v dd 0.85 v dd 0.85 v dd 0.85 v dd 0.7 v dd v dd v dd v dd v dd v dd v dd v dd v v v v v v v for all v dd (5) 4.0v < v dd 5.5v (5) v dd > 5.5v pic16cr54e-rc only (4) pic16cr54e-xt, 10, hs, lp hysteresis of schmitt trigger inputs v hys 0.15v dd *v input leakage current (2,3) i/o ports mclr t0cki osc1 i il ? ? ? ? 0.5 0.5 0.5 0.5 +1 +5 +3 +3 m a m a m a m a m a for v dd 5.5 v v ss v pin v dd , pin at hi-impedance v pin = v ss + 0.25v v pin = v dd v ss v pin v dd v ss v pin v dd , pic16cr54e-xt, 10, hs, lp output low voltage i/o ports osc2/clkout vol 0.6 0.6 v v i ol = 8.7 ma, v dd = 4.5v i ol = 1.6 ma, v dd = 4.5v, pic16cr54-rc output high voltage (3) i/o ports osc2/clkout v oh v dd ?.7 v dd ?.7 v v i oh = ?.4 ma, v dd = 4.5v i oh = ?.0 ma, v dd = 4.5v, pic16cr54-rc * these parameters are characterized but not tested. note 1: data in the typical (?yp? column is based on characterization results at 25 c. this data is for design guidance only and is not tested. 2: the leakage current on the mclr /v pp pin is strongly dependent on the applied voltage level. the speci?d levels represent normal operating conditions. higher leakage current may be measured at different input volt- age. 3: negative current is de?ed as coming out of the pin. 4: for pic16c5x-rc devices, the osc1/clkin pin is a schmitt trigger input. it is not recommended that the pic16c5x be driven with external clock in rc mode. 5: the user may use the better of the two speci?ations.
1995 microchip technology inc. ds30015m-page 85 pic16cr54 pic16c5x not recommended for new designs 12.5 timing p arameter symbology and load conditions the timing parameter symbols have been created following one of the following formats: 1. tpps2pps 2. tpps t f frequency t time lowercase subscripts (pp) and their meanings: pp 2 to mc mclr ck clkout osc oscillator cy cycle time os osc1 drt device reset timer t0 t0cki io i/o port wdt watchdog timer uppercase letters and their meanings: s f fall p period h high r rise i invalid (hi-impedance) v valid l low z hi-impedance figure 12-1: load conditions c l v ss pin c l = 50 pf for all pins except osc2 15 pf for osc2 in xt, hs or lp modes when external clock is used to drive osc1
pic16c5x pic16cr54 ds30015m-page 86 1995 microchip technology inc. not recommended for new designs 12.6 timing dia grams and speci cation s figure 12-2: external clock timing - pic16cr54 table 12-2: external clock timing requirements - pic16cr54 ac characteristics standard operating conditions (unless otherwise speci?d) operating temperature 0 c t a +70 c (commercial), ?0 c t a +85 c (industrial), ?0 c t a +125 c (automotive) operating voltage v dd range is described in section 12.1 and section 12.2 parameter no. sym characteristic min typ (1) max units conditions f osc external clkin frequency (2) dc 4 mhz rc osc mode dc 4 mhz xt osc mode dc 10 mhz 10 mhz mode dc 20 mhz hs osc mode (com/indust) dc 16 mhz hs osc mode (automotive) dc 200 khz lp osc mode oscillator frequency (2) dc 4 mhz rc osc mode 0.1 4 mhz xt osc mode 4 10 mhz 10 mhz mode 4 20 mhz hs osc mode (com/indust) 4 16 mhz hs osc mode (automotive) dc 200 khz lp osc mode * these parameters are characterized but not tested. note 1: data in the typical (?yp? column is at 5.0v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. 2: all speci?d values are based on characterization data for that particular oscillator type under standard operating condi- tions with the device executing code. exceeding these speci?d limits may result in an unstable oscillator operation and/or higher than expected current consumption. when an external clock input is used, the ?ax?cycle time limit is ?c?(no clock) for all devices. 3: instruction cycle period (t cy ) equals four times the input oscillator time base period. osc1 clkout q4 q1 q2 q3 q4 q1 133 44 2
1995 microchip technology inc. ds30015m-page 87 pic16cr54 pic16c5x not recommended for new designs 1t osc external clkin period (2) 250 ns rc osc mode 250 ns xt osc mode 100 ns 10 mhz mode 50 ns hs osc mode (com/indust) 62.5 ns hs osc mode (automotive) 5 m s lp osc mode oscillator period (2) 250 ns rc osc mode 250 10,000 ns xt osc mode 100 250 ns 10 mhz mode 50 250 ns hs osc mode (com/indust) 62.5 250 ns hs osc mode (automotive) 5 m s lp osc mode 2t cy instruction cycle time (3) 4/f osc 3 tosl, tosh clock in (osc1) low or high time 50* ns xt oscillator 20* ns hs oscillator 2* m s lp oscillator 4 tosr, tosf clock in (osc1) rise or fall time 25* ns xt oscillator 25* ns hs oscillator 50* ns lp oscillator table 12-2: external clock timing requirements - pic16cr54 (con?) ac characteristics standard operating conditions (unless otherwise speci?d) operating temperature 0 c t a +70 c (commercial), ?0 c t a +85 c (industrial), ?0 c t a +125 c (automotive) operating voltage v dd range is described in section 12.1 and section 12.2 parameter no. sym characteristic min typ (1) max units conditions * these parameters are characterized but not tested. note 1: data in the typical (?yp? column is at 5.0v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. 2: all speci?d values are based on characterization data for that particular oscillator type under standard operating condi- tions with the device executing code. exceeding these speci?d limits may result in an unstable oscillator operation and/or higher than expected current consumption. when an external clock input is used, the ?ax?cycle time limit is ?c?(no clock) for all devices. 3: instruction cycle period (t cy ) equals four times the input oscillator time base period.
pic16c5x pic16cr54 ds30015m-page 88 1995 microchip technology inc. not recommended for new designs figure 12-3: clkout and i/o timing - pic16cr54 table 12-3: clkout and i/o timing requirements - pic16cr54 ac characteristics standard operating conditions (unless otherwise speci?d) operating temperature 0 c t a +70 c (commercial), ?0 c t a +85 c (industrial), ?0 c t a +125 c (automotive) operating voltage v dd range is described in section 12.1 and section 12.2 parameter no. sym characteristic min typ (1) max units 10 tosh2ckl osc1 to clkout (2) 15 30** ns 11 tosh2ckh osc1 to clkout (2) 15 30** ns 12 tckr clkout rise time (2) 5 15** ns 13 tckf clkout fall time (2) 5 15** ns 14 tckl2iov clkout to port out valid (2) 40** ns 15 tiov2ckh port in valid before clkout (2) 0.25 t cy + 30* ns 16 tckh2ioi port in hold after clkout (2) 0* ns 17 tosh2iov osc1 (q1 cycle) to port out valid (3) 100* ns 18 tosh2ioi osc1 (q2 cycle) to port input invalid (i/o in hold time) tbd ns 19 tiov2osh port input valid to osc1 (i/o in setup time) tbd ns 20 tior port output rise time (3) 10 25** ns 21 tiof port output fall time (3) 10 25** ns * these parameters are characterized but not tested. ** these parameters are design targets and are not tested. no characterization data available at this time. note 1: data in the typical (?yp? column is at 5.0v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. 2: measurements are taken in rc mode where clkout output is 4 x t osc . 3: see figure 12-1 for loading conditions. osc1 clkout i/o pin (input) i/o pin (output) q4 q1 q2 q3 10 14 17 20, 21 18 15 11 16 old value new value note: all tests must be done with speci?d capacitive loads (see data sheet) 50 pf on i/o pins and clkout. 19 12 13
1995 microchip technology inc. ds30015m-page 89 pic16cr54 pic16c5x not recommended for new designs figure 12-4: reset, watchdog timer, and device reset timer timing - pic16cr54 table 12-4: reset, watchdog timer, and device reset timer - pic16cr54 ac characteristics standard operating conditions (unless otherwise speci?d) operating temperature 0 c t a +70 c (commercial), ?0 c t a +85 c (industrial), ?0 c t a +125 c (automotive) operating voltage v dd range is described in section 12.1 and section 12.2 parameter no. sym characteristic min typ (1) max units conditions 30 tmcl mclr pulse width (low) 100* ns v dd = 5.0v 31 twdt watchdog timer time-out period (no prescaler) 7* 18* 30* ms v dd = 5.0v (commercial) 32 t drt device reset timer period 7* 18* 30* ms v dd = 5.0v (commercial) 34 tio z i/o hi-impedance from mclr low 100* ns * these parameters are characterized but not tested. note 1: data in the typical (?yp? column is at 5.0v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. v dd mclr internal por drt time-out internal reset watchdog timer reset 32 31 34 i/o pin 32 32 34 (note 1) note 1: i/o pins must be taken out of hi-impedance mode by enabling the output drivers in software. 30
pic16c5x pic16cr54 ds30015m-page 90 1995 microchip technology inc. not recommended for new designs figure 12-5: timer0 clock timings - pic16cr54 table 12-5: timer0 clock requirements - pic16cr54 ac characteristics standard operating conditions (unless otherwise speci?d) operating temperature 0 c t a +70 c (commercial), ?0 c t a +85 c (industrial), ?0 c t a +125 c (automotive) operating voltage v dd range is described in section 12.1 and section 12.2 parameter no. sym characteristic min typ (1) max units conditions 40 tt0h t0cki high pulse width - no prescaler 0.5 t cy + 20* ns - with prescaler 10* ns 41 tt0l t0cki low pulse width - no prescaler 0.5 t cy + 20* ns - with prescaler 10* ns 42 tt0p t0cki period 20 or t cy + 40 * n ns whichever is greater. n = prescale value (1, 2, 4,..., 256) * these parameters are characterized but not tested. note 1: data in the typical (?yp? column is at 5.0v, 25?c unless otherwise stated. these parameters are for design guidance only and are not tested. t0cki 40 41 42
1995 microchip technology inc. ds30015m-page 91 pic16cr54 pic16c5x not recommended for new designs 13.0 dc and ac characteristics - pic16cr54 the graphs and tables provided in this section are for design guidance and are not tested or guaranteed. in some graphs or tables the data presented are outside speci?d operating range (e.g., outside speci?d v dd range). this is for information only and devices are will properly only within the speci?d range. the data presented in this section is a statistical summary of data collected on units from different lots over a period of time. ?ypical?represents the mean of the distribution while ?ax?or ?in?represents (mean + 3 s ) and (mean ?3 s ) respectively, where s is standard deviation. figure 13-1: typical rc oscillator frequency vs. temperature table 13-1: rc oscillator frequencies cext rext average fosc @ 5v, 25 c part to part variation 20 pf 3.3 k 6.02 mhz 28% 5 k 4.06 mhz 25% 10 k 2.47 mhz 24% 100 k 261 khz 39% 100 pf 3.3 k 1.82 mhz 18% 5 k 1.28 mhz 21% 10 k 715 khz 18% 100 k 72.4 khz 28% 300 pf 3.3 k 712.4 khz 14% 5 k 508 khz 13% 10 k 278 khz 13% 100 k 28 khz 23% measured on dip packages. the percentage variation indicated here is part-to-part variation due to normal process distribution. the variation indicated is 3 standard deviation from average value for full v dd range. f osc f osc (25 c) 1.10 1.08 1.06 1.04 1.02 1.00 0.98 0.96 0.94 0.92 0.90 010 20253040506070 t( c) frequency normalized to +25 c v dd = 5.5v v dd = 3.5v rext 10 k w cext = 100 pf 0.88 this document was created with framemake r404
pic16c5x pic16cr54 ds30015m-page 92 1995 microchip technology inc. not recommended for new designs figure 13-2: typical rc oscillator frequency vs. v dd , c ext = 20 p f 5.5 5.0 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd (volts) fosc (mhz) r = 5k r = 10k r = 100k 6.0 6.5 2.5 r = 3.3k measured on dip packages, t = 25?c figure 13-3: typical rc oscillator frequency vs. v dd , c ext = 100 p f 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd (volts) fosc (mhz) r = 3.3k r = 5k r = 10k r = 100k 2.5 measured on dip packages, t = 25?c
1995 microchip technology inc. ds30015m-page 93 pic16cr54 pic16c5x not recommended for new designs figure 13-4: typical rc oscillator frequency vs. v dd , c ext = 300 p f 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd (volts) f osc (mhz) r = 3.3k r = 5k r = 10k r = 100k 2.5 measured on dip packages, t = 25?c figure 13-5: typical i pd vs. v dd , watchdog enabled figure 13-6: maximum i pd vs. v dd , watchdog enabled 0.01 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 i pd ( m a) v dd (volts) 0.1 6.0 1.0 10 t = 25?c 30 20 10 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i pd ( m a) v dd (volts) 5 15 25 35 2.0 ?0 c +85 c
pic16c5x pic16cr54 ds30015m-page 94 1995 microchip technology inc. not recommended for new designs figure 13-7: v th (input threshold voltage) of i/o pins vs. v dd figure 13-8: v ih , v il of mclr , t0cki and osc1 (in rc mode) vs. v dd figure 13-9: v th (input threshold voltage) of osc1 input (in xt, hs, and lp modes) vs. v dd 2.00 1.80 1.60 1.40 1.20 1.00 2.5 3.0 3.5 4.0 4.5 5.0 v dd (volts) min (?0 c to +85 c) 0.80 0.60 5.5 6.0 max (?0 c to +85 c) typ (+25 c) v th (volts) 3.5 3.0 2.5 2.0 1.5 1.0 2.5 3.0 3.5 4.0 4.5 5.0 v dd (volts) 0.5 0.0 5.5 6.0 v ih , v il (volts) 4.0 4.5 v ih min (?0 c to +85 c) v ih max (?0 c to+ 85 c) v ih typ +25 c v il min (?0 c to +85 c) v il max (?0 c to +85 c) v il typ +25 c note: these input pins have schmitt trigger input buffers. 2.4 2.2 2.0 1.8 1.6 1.4 2.5 3.0 3.5 4.0 4.5 5.0 v dd (volts) 1.2 1.0 5.5 6.0 typ (+25 c) v th (volts) 2.6 2.8 3.0 3.2 3.4 max (?0 c to +85 c) min (?0 c to +85 c)
1995 microchip technology inc. ds30015m-page 95 pic16cr54 pic16c5x not recommended for new designs figure 13-10: typical i dd vs. frequency (external clock 25 c) external clock frequency (hz) 10 1.0 0.1 0.01 0.001 10k 100k 1m 10m idd (ma) 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5
pic16c5x pic16cr54 ds30015m-page 96 1995 microchip technology inc. not recommended for new designs figure 13-11: maximum i dd vs. frequency (external clock ?0 c to +85 c) external clock frequency (hz) 10000 1000 100 10 10k 100k 1m 10m i dd ( m a) 6.0 5.5 5.0 4.5 4.0 3.5 3.0 2.5
1995 microchip technology inc. ds30015m-page 97 pic16cr54 pic16c5x not recommended for new designs figure 13-12: wdt timer time-out period vs. v dd 50 45 40 35 30 25 20 15 10 5 234567 v dd (volts) wdt period (ms) max +85 c max +70 c typ +25 c min 0 c min ?0 c figure 13-13: transconductance (gm) of hs oscillator vs. v dd 9000 8000 7000 6000 5000 4000 3000 2000 100 0 234567 v dd (volts) gm ( m a/v) min +85 c max ?0 c typ +25 c
pic16c5x pic16cr54 ds30015m-page 98 1995 microchip technology inc. not recommended for new designs figure 13-14: transconductance (gm) of lp oscillator vs. v dd figure 13-15: transconductance (gm) of xt oscillator vs. v dd 45 40 35 30 25 20 15 10 5 0 234567 v dd (volts) gm ( m a/v) min +85 c typ +25 c max ?0 c 2500 2000 1500 1000 500 0 234567 v dd (volts) gm ( m a/v) min +85 c max ?0 c typ +25 c figure 13-16: i oh vs. v oh , v dd = 3 v figure 13-17: i oh vs. v oh , v dd = 5 v 0 ? ?0 ?5 ?0 ?5 0.0 0.5 1.0 1.5 2.0 2.5 v oh (volts) i oh (ma) 3.0 typ +25 c max ?0 c min +85 c 0 ?0 ?0 ?0 ?0 1.5 2.0 2.5 3.0 3.5 4.0 v oh (volts) i oh (ma) max ?0 c 4.5 5.0 typ +25 c ? ?5 ?5 ?5 min +85 c
1995 microchip technology inc. ds30015m-page 99 pic16cr54 pic16c5x not recommended for new designs figure 13-18: i ol vs. v ol , v dd = 3 v 45 40 35 30 25 20 15 10 5 0 0.0 0.5 1.0 1.5 2.0 2.5 v ol (volts) i ol (ma) min +85 c max ?0 c typ +25 c 3.0 figure 13-19: i ol vs. v ol , v dd = 5 v table 13-2: input capacitance for pic16cr54 pin typical capacitance (pf) 18l pdip 18l soic ra, rb port 5.0 4.3 mclr 2.0 2.0 osc1, osc2/clkout 4.0 3.5 t0cki 3.2 2.8 all capacitance values are typical at 25 c. a part-to-part variation of 25% (three standard deviations) should be taken into account. 90 80 70 60 50 40 30 20 10 0 0.0 0.5 1.0 1.5 2.0 2.5 v ol (volts) i ol (ma) min +85 c max ?0 c typ +25 c 3.0
pic16c5x pic16cr54 ds30015m-page 100 1995 microchip technology inc. not recommended for new designs notes:
1995 microchip technology inc. ds30015m-page 101 pic16c5x 14.0 packaging information 14.1 p ac ka g e marking inf ormation mmmmmmmmmmmmxxx mmmmmmmmxxxxxxx aabb cde 18-lead pdip 28-lead skinny pdip (.300") xxxxxxxxxxxxxxxxx aabb cde mmmmmmmmmmmmmmmmm pic16c56- rci/p456 9523 cba example example rci/p456 9523 cba pic16c55- legend: mm...m microchip part number information xx...x customer speci? information* aa year code (last two digits of calendar year) bb week code (week of january 1 is week ?1? c facility code of the plant at which wafer is manufactured c = chandler, arizona, u.s.a., s = tempe, arizona, u.s.a. d mask revision number e assembly code of the plant or country of origin in which part was assembled note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer speci? information. * standard otp marking consists of microchip part number, year code, week code, facility code, mask rev#, and assembly code. for otp marking beyond this, certain price adders apply. please check with your microchip sales of?e. for qtp devices, any special marking adders are included in qtp price. mmmmmmmmxxxxxxx xxxxxxxxxxxxxxx aabb cde 28-lead pdip (.600") mmmmmmmmmmmmxxx xti/p126 9542 cda example pic16c55- this document was created with framemake r404
pic16c5x ds30015m-page 102 1995 microchip technology inc. legend: mm...m microchip part number information xx...x customer speci? information* aa year code (last two digits of calendar year) bb week code (week of january 1 is week ?1? c facility code of the plant at which wafer is manufactured c = chandler, arizona, u.s.a., s = tempe, arizona, u.s.a. d mask revision number e assembly code of the plant or country of origin in which part was assembled note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer speci? information. * standard otp marking consists of microchip part number, year code, week code, facility code, mask rev#, and assembly code. for otp marking beyond this, certain price adders apply. please check with your microchip sales of?e. for qtp devices, any special marking adders are included in qtp price. 18-lead soic mmmmmmmmm aabb cde xxxxxxxxx 28-lead soic xxxxxxxxxxxxxxxxxxxx aabb cde mmmmmmmmmmmmmmmmmmxx 20-lead ssop xxxxxxxx aabb cde mmmmmmmm example pic16c54- 9518 cdk xti/s0218 example 9515 cbk pic16c57-xt/so example xti/218 9520 cbp pic16c54 28-lead ssop xxxxxxxxxxxx aabb cde mmmmmmmmmmmm example 9525 cbk pic16c57- xt/ss123
1995 microchip technology inc. ds30015m-page 103 pic16c5x mmmmmmmm mmmmmmmm aabb cde 18-lead cerdip windowed 28-lead cerdip windowed mmmmmmmmmm mmmmmm aabb cde 9501 cba example example 9538 cba legend: mm...m microchip part number information xx...x customer speci? information* aa year code (last two digits of calendar year) bb week code (week of january 1 is week ?1? c facility code of the plant at which wafer is manufactured c = chandler, arizona, u.s.a., s = tempe, arizona, u.s.a. d mask revision number e assembly code of the plant or country of origin in which part was assembled note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer speci? information. * standard otp marking consists of microchip part number, year code, week code, facility code, mask rev#, and assembly code. for otp marking beyond this, certain price adders apply. please check with your microchip sales of?e. for qtp devices, any special marking adders are included in qtp price. pic16c54 /jw pic16c57 /jw mmmmmmmmmmmmmm xxxxxxxxxxxxxx aabbcde 28-lead cerdip skinny windowed pic16c57 /jw 9338 cct example
pic16c5x ds30015m-page 104 1995 microchip technology inc. 14.2 18-lead plastic dual in- li ne (pdip) - 3 00 mil package group: plastic dual in-line (pla) symbol millimeters inches min max notes min max notes a 0 10 0 10 a 4.064 0.160 a1 0.381 0.015 a2 3.048 3.810 0.120 0.150 b 0.355 0.559 0.014 0.022 b1 1.524 1.524 reference 0.060 0.060 reference c 0.203 0.381 typical 0.008 0.015 typical d 22.479 23.495 0.885 0.925 d1 20.320 20.320 reference 0.800 0.800 reference e 7.620 8.255 0.300 0.325 e1 6.096 7.112 0.240 0.280 e1 2.489 2.591 typical 0.098 0.102 typical ea 7.620 7.620 reference 0.300 0.300 reference eb 7.874 9.906 0.310 0.390 l 3.048 3.556 0.120 0.140 n 1818 1818 s 0.889 0.035 s1 0.127 0.005 n pin no. 1 indicator area e1 e s d b1 b d1 base plane seating plane s1 a1 a2 a l e1 a c e a e b
1995 microchip technology inc. ds30015m-page 105 pic16c5x 14.3 28-lead plastic dual in- li ne (pdip) - 3 00 mil package group: plastic dual in-line (pla) symbol millimeters inches min max notes min max notes a 0 10 0 10 a 3.632 4.572 0.143 0.180 a1 0.381 0.015 a2 3.175 3.556 0.125 0.140 b 0.406 0.559 0.016 0.022 b1 1.016 1.651 typical 0.040 0.065 typical b2 0.762 1.016 4 places 0.030 0.040 4 places b3 0.203 0.508 4 places 0.008 0.020 4 places c 0.203 0.331 typical 0.008 0.013 typical d 34.163 35.179 1.385 1.395 d1 33.020 33.020 reference 1.300 1.300 reference e 7.874 8.382 0.310 0.330 e1 7.112 7.493 0.280 0.295 e1 2.540 2.540 typical 0.100 0.100 typical ea 7.874 7.874 reference 0.310 0.310 reference eb 8.128 9.652 0.320 0.380 l 3.175 3.683 0.125 0.145 n 28 - 28 - s 0.584 1.220 0.023 0.048 n pin no. 1 indicator area e1 e s d d1 base plane seating plane a1 a2 a l e1 a c e a e b detail a detail a b2 b1 b b3
pic16c5x ds30015m-page 106 1995 microchip technology inc. 14.4 28-lead plastic dual in- li ne ( pdip) - 600 mil package group: plastic dual in-line (pla) symbol millimeters inches min max notes min max notes a 0 10 0 10 a 5.080 0.200 a1 0.508 0.020 a2 3.175 4.064 0.125 0.160 b 0.355 0.559 0.014 0.022 b1 1.270 1.778 typical 0.050 0.070 typical c 0.203 0.381 typical 0.008 0.015 typical d 35.052 37.084 1.380 1.460 d1 33.020 33.020 reference 1.300 1.300 reference e 15.240 15.875 0.600 0.625 e1 12.827 13.970 0.505 0.550 e1 2.489 2.591 typical 0.098 0.102 typical ea 15.240 15.240 reference 0.600 0.600 reference eb 15.240 17.272 0.600 0.680 l 2.921 3.683 0.115 0.145 n 2828 2828 s 0.889 0.035 s1 0.508 0.020 n pin no. 1 indicator area e1 e s d b1 b d1 base plane seating plane s1 a1 a2 a l e1 a c e a e b
1995 microchip technology inc. ds30015m-page 107 pic16c5x 14.5 18-lead plastic surface mount (soic ) - 3 00 mil package group: plastic soic (so) symbol millimeters inches min max notes min max notes a 0 8 0 8 a 2.362 2.642 0.093 0.104 a1 0.101 0.300 0.004 0.012 b 0.355 0.483 0.014 0.019 c 0.241 0.318 0.009 0.013 d 11.353 11.735 0.447 0.462 e 7.416 7.595 0.292 0.299 e 1.270 1.270 reference 0.050 0.050 reference h 10.007 10.643 0.394 0.419 h 0.381 0.762 0.015 0.030 l 0.406 1.143 0.016 0.045 n 1818 1818 cp 0.102 0.004 b e n index area chamfer h x 45 a e h 1 2 3 cp h x 45 c l seating plane base plane d a1 a
pic16c5x ds30015m-page 108 1995 microchip technology inc. 14.6 28-lead plastic surface mount (soic ) - 3 00 mil package group: plastic soic (so) symbol millimeters inches min max notes min max notes a 0 8 0 8 a 2.362 2.642 0.093 0.104 a1 0.101 0.300 0.004 0.012 b 0.355 0.483 0.014 0.019 c 0.241 0.318 0.009 0.013 d 17.703 18.085 0.697 0.712 e 7.416 7.595 0.292 0.299 e 1.270 1.270 typical 0.050 0.050 typical h 10.007 10.643 0.394 0.419 h 0.381 0.762 0.015 0.030 l 0.406 1.143 0.016 0.045 n 2828 2828 cp 0.102 0.004 b e n index area chamfer h x 45 a e h 1 2 3 cp h x 45 c l seating plane base plane d a1 a
1995 microchip technology inc. ds30015m-page 109 pic16c5x 14.7 20-lead plastic surface mount (ssop) - 209 mil package group: plastic ssop symbol millimeters inches min max notes min max notes a 0 8 0 8 a 1.730 1.990 0.068 0.078 a1 0.050 0.210 0.002 0.008 b 0.250 0.380 0.010 0.015 c 0.130 0.220 0.005 0.009 d 7.070 7.330 0.278 0.289 e 5.200 5.380 0.205 0.212 e 0.650 0.650 reference 0.026 0.026 reference h 7.650 7.900 0.301 0.311 l 0.550 0.950 0.022 0.037 n 2020 2020 cp - 0.102 - 0.004 index area n h 123 e e b cp d a a1 base plane seating plane l c a
pic16c5x ds30015m-page 110 1995 microchip technology inc. 14.8 28-lead plastic surface mount (ssop) - 209 mil package group: plastic ssop symbol millimeters inches min max notes min max notes a 0 8 0 8 a 1.730 1.990 0.068 0.078 a1 0.050 0.210 0.002 0.008 b 0.250 0.380 0.010 0.015 c 0.130 0.220 0.005 0.009 d 10.070 10.330 0.396 0.407 e 5.200 5.380 0.205 0.212 e 0.650 0.650 reference 0.026 0.026 reference h 7.650 7.900 0.301 0.311 l 0.550 0.950 0.022 0.037 n 2828 2828 cp - 0.102 - 0.004 index area n h 123 e e b cp d a a1 base plane seating plane l c a
1995 microchip technology inc. ds30015m-page 111 pic16c5x 14.9 18-lead ceramic d ual in- li ne (cerdip) with windo w - 3 00 mil package group: ceramic dual in-line (cdp) symbol millimeters inches min max notes min max notes a 0 10 0 10 a 5.080 0.200 a1 0.381 1.7780 0.015 0.070 a2 3.810 4.699 0.150 0.185 a3 3.810 4.445 0.150 0.175 b 0.355 0.585 0.014 0.023 b1 1.270 1.651 typical 0.050 0.065 typical c 0.203 0.381 typical 0.008 0.015 typical d 22.352 23.622 0.880 0.930 d1 20.320 20.320 reference 0.800 0.800 reference e 7.620 8.382 0.300 0.330 e1 5.588 7.874 0.220 0.310 e1 2.540 2.540 reference 0.100 0.100 reference ea 7.366 8.128 typical 0.290 0.320 typical eb 7.620 10.160 0.300 0.400 l 3.175 3.810 0.125 0.150 n 1818 1818 s 0.508 1.397 0.020 0.055 s1 0.381 1.270 0.015 0.050 n pin no. 1 indicator area e1 e s d b1 b d1 base plane seating plane s1 a1 a3 a l a c e a e b e1 a2
pic16c5x ds30015m-page 112 1995 microchip technology inc. 14.10 28-lead ceramic dual in-line (cerdip) with windo w - 300 mil) package group: ceramic dual in-line (cdp) symbol millimeters inches min max notes min max notes a 0 10 0 10 a 3.30 5.84 .130 0.230 a1 0.38 0.015 a2 2.92 4.95 0.115 0.195 b 0.35 0.58 0.014 0.023 b1 1.14 1.78 typical 0.045 0.070 typical c 0.20 0.38 typical 0.008 0.015 typical d 34.54 37.72 1.360 1.485 d2 32.97 33.07 reference 1.298 1.302 reference e 7.62 8.25 0.300 0.325 e1 6.10 7.87 0.240 0.310 e 2.54 2.54 typical 0.100 0.100 typical ea 7.62 7.62 reference 0.300 0.300 reference eb 11.43 0.450 l 2.92 5.08 0.115 0.200 n 2828 2828 d1 0.13 0.005 n pin no. 1 indicator area e1 e d b1 b d2 base plane seating plane d1 a1 a2 a l e1 a c e a e b
1995 microchip technology inc. ds30015m-page 113 pic16c5x 14.11 28-lead ceramic d ual in- li ne (cerdip) with windo w - 6 00 mil package group: ceramic dual in-line (cdp) symbol millimeters inches min max notes min max notes a 0 10 0 10 a 5.461 0.215 a1 0.381 1.524 0.015 0.060 a2 3.810 4.699 0.150 0.185 a3 3.810 4.445 0.150 0.175 b 0.355 0.585 0.014 0.023 b1 1.270 1.651 typical 0.050 0.065 typical c 0.203 0.381 typical 0.008 0.015 typical d 36.195 37.465 1.425 1.475 d1 33.020 33.020 reference 1.300 1.300 reference e 15.240 15.875 0.600 0.625 e1 12.954 15.240 0.510 0.600 e1 2.540 2.540 typical 0.100 0.100 typical ea 14.986 15.748 reference 0.590 0.620 reference eb 15.240 18.034 0.600 0.710 l 3.175 3.810 0.125 0.150 n 2828 2828 s 1.016 2.286 0.040 0.090 s1 0.381 1.778 0.015 0.070 n pin no. 1 indicator area e1 e s d b1 b d1 base plane seating plane s1 a1 a3 a a2 l e1 a c e a e b
pic16c5x ds30015m-page 114 1995 microchip technology inc. notes:
1995 microchip technology inc. ds30015m-page 115 pic16c5x appendix a: compatibility to convert code written for pic16cxx to pic16c5x, the user should take the following steps: 1. check any call , goto or instructions that modify the pc to determine if any program memory page select operations (pa2, pa1, pa0 bits) need to be made. 2. revisit any computed jump operations (write to pc or add to pc, etc.) to make sure page bits are set properly under the new scheme. 3. eliminate any special function register page switching. rede?e data variables to reallocate them. 4. verify all writes to status, option, and fsr registers since these have changed. 5. change reset vector to proper value for processor used. 6. remove any use of the addlw and sublw instructions. 7. rewrite any code segments that use interrupts. appendix b: whats new b.1 format the format of this data sheet has been changed to be consistent with other product families. this ensures that important topics are covered across all pic16/17 families. here is an overview list of new features: data sheet structure / outline consistent figures and tables b.2 ad ditions items that have been added to this data sheet are: pic16cr54 data pic16c5x-10 data pic16c5x/jw package information this document was created with framemake r404
pic16c5x ds30015m-page 116 1995 microchip technology inc. appendix c: whats changed changes to this version of the pic16c5x data sheet are: correction of the 28-lead ssop package pin-out inclusion of errata sheet information
1995 microchip technology inc. ds30390b-page 117 pic16c7x appendix d: pic16/17 microcontrollers table d-1: pic16c5x family of devices pic16c54 20 512 25 tmr0 12 2.5-6.25 33 18-pin dip, soic; 20-pin ssop pic16c54a 20 512 25 tmr0 12 2.5-6.25 33 18-pin dip, soic; 20-pin ssop pic16cr54 (2) 20 512 25 tmr0 12 2.0-6.25 33 18-pin dip, soic; 20-pin ssop pic16cr54a 20 512 25 tmr0 12 2.0-6.25 33 18-pin dip, soic; 20-pin ssop pic16cr54b (1) 20 512 25 tmr0 12 2.5-6.25 33 18-pin dip, soic; 20-pin ssop pic16c55 20 512 24 tmr0 20 2.5-6.25 33 28-pin dip, soic, ssop pic16c56 20 1k 25 tmr0 12 2.5-6.25 33 18-pin dip, soic; 20-pin ssop pic16cr56 (1) 20 1k 25 tmr0 12 2.5-6.25 33 18-pin dip, soic; 20-pin ssop pic16c57 20 2k 72 tmr0 20 2.5-6.25 33 28-pin dip, soic, ssop pic16cr57a (2) 20 2k 72 tmr0 20 2.5-6.25 33 28-pin dip, soic, ssop pic16cr57b 20 2k 72 tmr0 20 2.5-6.25 33 28-pin dip, soic, ssop pic16c58a 20 2k 73 tmr0 12 2.5-6.25 33 18-pin dip, soic; 20-pin ssop pic16cr58a 20 2k 73 tmr0 12 2.5-6.25 33 18-pin dip, soic; 20-pin ssop pic16cr58b (1) 20 2k 73 tmr0 12 2.5-6.25 33 18-pin dip, soic; 20-pin ssop all pic16/17 family devices have power-on reset, selectable watchdog timer, selectable code protect and high i/o current capability. note 1: please contact your local sales of?e for availability of these devices. 2: not recommended for new designs. maximum frequency of operation (mhz) eprom rom ram data memory (bytes) timer module(s) i/o pins voltage range (volts) number of instructions packages program memory clock memory peripherals features (words) this document was created with framemake r404
pic16c7x ds30390b-page 118 1995 microchip technology inc. table d-2: pic16c62x family of devices pic16c620 20 512 80 tmr0 2 yes 4 13 3.0-6.0 yes yes 18-pin dip, soic; 20-pin ssop pic16c621 20 1k 80 tmr0 2 yes 4 13 3.0-6.0 yes yes 18-pin dip, soic; 20-pin ssop pic16c622 20 2k 128 tmr0 2 yes 4 13 3.0-6.0 yes yes 18-pin dip, soic; 20-pin ssop all pic16/17 family devices have power-on reset, selectable watchdog timer, selectable code protect and high i/o current capability. all pic16cxx family devices use serial programming with clock pin rb6 and data pin rb7. maximum frequency of operation (mhz) eprom data memory (bytes) timer module(s) comparator(s) internal reference voltage interrupt sources i/o pins voltage range (volts) brown-out reset packages program memory clock memory peripherals features in-circuit serial programming
1995 microchip technology inc. ds30390b-page 119 pic16c7x table d-3: pic16c6x family of devices pic16c61 20 1k 36 tmr0 3 13 3.0-6.0 yes 18-pin dip, soic pic16c62 20 2k 128 tmr0, tmr1, tmr2 1 spi/i 2 c 7 22 3.0-6.0 yes 28-pin sdip, soic, ssop pic16c62a (1) 20 2k 128 tmr0, tmr1, tmr2 1 spi/i 2 c 7 22 3.0-6.0 yes yes 28-pin sdip, soic, ssop pic16cr62 (1) 20 2k 128 tmr0, tmr1, tmr2 1 spi/i 2 c 7 22 3.0-6.0 yes yes 28-pin sdip, soic, ssop pic16c63 (1) 20 4k 192 tmr0, tmr1, tmr2 2 spi/i 2 c, usart 10 22 3.0-6.0 yes yes 28-pin sdip, soic pic16c64 20 2k 128 tmr0, tmr1, tmr2 1 spi/i 2 c yes 8 33 3.0-6.0 yes 40-pin dip; 44-pin plcc, mqfp pic16c64a (1) 20 2k 128 tmr0, tmr1, tmr2 1 spi/i 2 c yes 8 33 3.0-6.0 yes yes 40-pin dip; 44-pin plcc, mqfp, tqfp pic16cr64 (1) 20 2k 128 tmr0, tmr1, tmr2 1 spi/i 2 c yes 8 33 3.0-6.0 yes yes 40-pin dip; 44-pin plcc, mqfp pic16c65 20 4k 192 tmr0, tmr1, tmr2 2 spi/i 2 c, usart yes 11 33 3.0-6.0 yes 40-pin dip; 44-pin plcc, mqfp pic16c65a (1) 20 4k 192 tmr0, tmr1, tmr2 2 spi/i 2 c, usart yes 11 33 3.0-6.0 yes yes 40-pin dip; 44-pin plcc, mqfp, tqfp all pic16/17 family devices have power-on reset, selectable watchdog timer, selectable code protect, and high i/o current capability. all pic16cxx family devices use serial programming with clock pin rb6 and data pin rb7. note 1: please contact your local sales of?e for availability of these devices. maximum frequency of operation (mhz) eprom data memory (bytes) timer module(s) capture/compare/pwm module(s) serial port(s) (spi/i 2 c, usart) parallel slave port interrupt sources i/o pins voltage range (volts) brown-out reset packages program memory clock memory peripherals features rom in-circuit serial programming
pic16c7x ds30390b-page 120 1995 microchip technology inc. table d-4: pic16c7x family of devices pic16c70 (1) 20 512 36 tmr0 4 4 13 3.0-6.0 yes yes 18-pin dip, soic; 20-pin ssop pic16c71 20 1k 36 tmr0 4 4 13 3.0-6.0 yes 18-pin dip, soic pic16c71a (1) 20 1k 68 tmr0 4 4 13 3.0-6.0 yes yes 18-pin dip, soic; 20-pin ssop pic16c72 (1) 20 2k 128 tmr0, tmr1, tmr2 1 spi/i 2 c 5 8 22 3.0-6.0 yes yes 28-pin sdip, soic, ssop pic16c73 20 4k 192 tmr0, tmr1, tmr2 2 spi/i 2 c, usart 5 11 22 3.0-6.0 yes 28-pin sdip, soic pic16c73a (1) 20 4k 192 tmr0, tmr1, tmr2 2 spi/i 2 c, usart 5 11 22 3.0-6.0 yes yes 28-pin sdip, soic pic16c74 20 4k 192 tmr0, tmr1, tmr2 2 spi/i 2 c, usart yes 8 12 33 3.0-6.0 yes 40-pin dip; 44-pin plcc, mqfp pic16c74a (1) 20 4k 192 tmr0, tmr1, tmr2 2 spi/i 2 c, usart yes 8 12 33 3.0-6.0 yes yes 40-pin dip; 44-pin plcc, mqfp, tqfp all pic16/17 family devices have power-on reset, selectable watchdog timer, selectable code protect and high i/o current capability. all pic16cxx family devices use serial programming with clock pin rb6 and data pin rb7. note 1: please contact your local sales of?e for availability of these devices. maximum frequency of operation (mhz) eprom data memory (bytes) timer module(s) capture/compare/pwm module(s) serial port(s) (spi/i 2 c, usart) parallel slave port a/d converter (8-bit) channels interrupt sources i/o pins voltage range (volts) brown-out reset packages program memory clock memory peripherals features in-circuit serial programming
1995 microchip technology inc. ds30390b-page 121 pic16c7x table d-5: pic16c8x family of devices pic16c83 (1) 10 512 36 64 tmr0 4 13 yes 2.0-6.0 18-pin dip, soic pic16cr83 (1) 10 512 36 64 tmr0 4 13 yes 2.0-6.0 18-pin dip, soic pic16c84 10 1k 36 64 tmr0 4 13 yes 2.0-6.0 18-pin dip, soic pic16c84a (1) 10 1k 68 64 tmr0 4 13 yes 2.0-6.0 18-pin dip, soic pic16cr84 (1) 10 1k 68 64 tmr0 4 13 yes 2.0-6.0 18-pin dip, soic all pic16/17 family devices have power-on reset, selectable watchdog timer, selectable code protect, and high i/o current capability. all pic16cxx family devices use serial programming with clock pin rb6 and data pin rb7. note 1: please contact your local sales of?e for availability of these devices. maximum frequency of operation (mhz) eeprom data eeprom (bytes) data memory (bytes) timer module(s) interrupt sources i/o pins voltage range (volts) packages program memory clock memory peripherals features rom in-circuit serial programming
pic16c7x ds30390b-page 122 1995 microchip technology inc. table d-6: pic17cxx family of devices pic17c42 25 2k 232 tmr0,tmr1, tmr2,tmr3 2 2 yes yes 11 33 4.5-5.5 yes yes 55 40-pin dip; 44-pin plcc, mqfp pic17c43 25 4k 454 tmr0,tmr1, tmr2,tmr3 2 2 yes yes 11 33 2.5-6.0 yes yes 58 40-pin dip; 44-pin plcc, tqfp pic17c44 25 8k 454 tmr0,tmr1, tmr2,tmr3 2 2 yes yes 11 33 2.5-6.0 yes yes 58 40-pin dip; 44-pin plcc, tqfp all pic16/17 family devices have power-on reset, selectable watchdog timer, selectable code protect and high i/o current capability. maximum frequency of operation (mhz) eprom ram data memory (bytes) timer module(s) captures serial port(s) (usart) external interrupts interrupt sources i/o pins voltage range (volts) number of instructions packages program memory clock memory peripherals features pwms in-circuit serial programming single instruction multiply
1995 microchip technology inc. ds30390b-page 123 pic16c7x d.1 pin compatibility devices that have the same package type and v dd , v ss and mclr pin locations are said to be pin compatible. this allows these different devices to operate in the same socket. compatible devices may only requires minor software modi?ation to allow proper operation in the application socket (ex., pic16c56 and pic16c61 devices). not all devices in the same package size are pin compatible; for example, the pic16c62 is compatible with the pic16c63, but not the pic16c55. pin compatibility does not mean that the devices offer the same features. as an example, the pic16c54 is pin compatible with the pic16c71, but does not have an a/d converter, weak pull-ups on portb, or interrupts. table d-7: pin compatible devices pin compatible devices package pic16c54, pic16c54a, pic16cr54, pic16cr54a, pic16cr54b, pic16c56, pic16cr56, pic16c58a, pic16cr58a, pic16cr58b, pic16c61, pic16c620, pic16c621, pic16c622, pic16c70, pic16c71, pic16c71a pic16c83, pic16cr83, pic16c84, pic16c84a, pic16cr84 18 pin (20 pin) pic16c55, pic16cr55, pic16c57, pic16cr57a, pic16cr57b 28 pin pic16c62, pic16cr62, pic16c62a, pic16c63, pic16c72, pic16c73, pic16c73a 28 pin pic16c64, pic16cr64, pic16c64a, pic16c65, pic16c65a, pic16c74, pic16c74a 40 pin pic17c42, pic17c43, pic17c44 40 pin
pic16c7x ds30390b-page 124 1995 microchip technology inc. notes:
1995 microchip technology inc. ds30015m-page 125 pic16c5x index a absolute maximum ratings ............................................... 57 alu ...................................................................................... 7 applications .......................................................................... 3 architectural overview ......................................................... 7 assembler .......................................................................... 54 b block diagram on-chip reset circuit ................................................ 31 pic16c5x series ......................................................... 8 timer0 ........................................................................ 23 tmr0/wdt prescaler ................................................ 26 watchdog timer ......................................................... 35 brown-out protection circuit ............................................. 36 c c compiler (mp-c) ...................................................... 51, 55 carry .................................................................................... 7 clocking scheme ............................................................... 11 code protection ........................................................... 27, 37 configuration bits ............................................................... 27 configuration word pic16c54/cr54/c55/c56/c57 ................................. 27 d dc characteristics ..................................... 59, 60, 61, 62, 63 development support ........................................................ 51 development systems ....................................................... 55 development tools ............................................................ 51 device drawings 18-lead ceramic dual in-line (cerdip) with window - 300 mil .............................................. 111 18-lead plastic dual in-line (pdip) - 300 mil ......... 104 18-lead plastic surface mount (soic) - 300 mil ..... 107 20-lead plastic surface mount (ssop) - 209 mil .... 109 28-lead ceramic cerdip dual in-line with window (300 mil)) ............................................. 112 28-lead ceramic dual in-line (cerdip) with window - 600 mil .............................................. 113 28-lead plastic dual in-line (pdip) - 300 mil ......... 105 28-lead plastic dual in-line (pdip) - 600 mil ......... 106 28-lead plastic surface mount (soic) - 300 mil ..... 108 28-lead plastic surface mount (ssop) - 209 mil .... 110 device varieties ................................................................... 5 digit carry ............................................................................ 7 dynamic data exchange (dde) ........................................ 51 e electrical characteristics .................................................... 57 external power-on reset circuit ....................................... 32 f family of devices ................................................................. 4 pic16c5x ................................................................ 117 pic17cxx ................................................................ 122 features ............................................................................... 1 fsr .............................................................................. 20, 31 fuzzy logic dev. system ( fuzzy tech -mp) ............. 51, 55 i i/o interfacing .................................................................... 21 i/o ports ............................................................................ 21 i/o programming considerations ...................................... 22 id locations ....................................................................... 37 id locations ........................................................................ 27 indf ............................................................................ 20, 31 indirect data addressing ................................................... 20 instruction cycle ................................................................ 11 instruction flow/pipelining ................................................. 11 instruction set summary ................................................... 40 integrated .......................................................................... 54 l loading of pc .................................................................... 18 loading of pc branch instructions .................................... 18 m mclr ................................................................................ 31 memory organization ........................................................ 13 data memory ............................................................. 13 program memory ....................................................... 13 mpasm assembler ..................................................... 51, 54 mp-c c compiler .............................................................. 55 mpsim software simulator ......................................... 51, 55 o one-time-programmable (otp) devices ............................5 option register .............................................................. 17 osc selection .................................................................... 27 oscillator configurations ................................................... 28 oscillator types hs .............................................................................. 28 lp .............................................................................. 28 rc ............................................................................. 28 xt .............................................................................. 28 p packaging information ..................................................... 101 pcl .................................................................................... 31 pic16c5x dc and ac characteristics .............................. 71 picdem-1 low-cost pic16/17 demo board .............. 51, 53 picdem-2 low-cost pic16cxx demo board ............ 51, 53 picmaster probes ......................................................... 52 picmaster system configuration .................................. 51 picmaster rt in-circuit emulator .............................. 51 picstart low-cost development system ............. 51, 53 pin compatible devices .................................................. 123 pinout description ......................................................... 9, 10 por oscillator start-up timer (ost) .................... 27, 32, 34 pd ........................................................................ 30, 36 power-on reset (por) ................................. 27, 31, 32 to ........................................................................ 30, 36 porta ........................................................................ 21, 31 portb ........................................................................ 21, 31 portc ........................................................................ 21, 31 power-down mode ............................................................ 37 prescaler ........................................................................... 26 pro mate universal programmer .......................... 51, 53 q quick-turnaround-production (qtp) devices ......................5 this document was created with framemake r404
pic16c5x ds30015m-page 126 1995 microchip technology inc. r rc oscillator ...................................................................... 30 read modify write .............................................................. 22 reset ............................................................................ 27, 30 reset on brown-out ........................................................... 36 s serialized quick-turnaround-production (sqtp) devices .. 5 sleep .......................................................................... 27, 37 software simulator (mpsim) .............................................. 55 special features of the cpu .............................................. 27 status ......................................................................... 7, 31 status word register ..................................................... 16 summary of port registers ................................................ 21 t timer0 switching prescaler assignment ................................ 26 timer0 ........................................................................ 23 timer0 (tmr0) module .............................................. 23 tmr0 with external clock .......................................... 25 timing diagrams and specifications ............................ 65, 86 timing parameter symbology and load conditions .... 64, 85 tris registers ................................................................... 21 u uv erasable devices ........................................................... 5 w w ........................................................................................ 31 wake-up from sleep ........................................................ 37 watchdog timer (wdt) ............................................... 27, 34 period ......................................................................... 34 programming considerations .................................... 34 z zero bit ................................................................................. 7 list of examples example 3-1: instruction pipeline flow ............................ 11 example 4-1: indirect addressing..................................... 20 example 4-2: how to clear ram using indirect addressing ................................................. 20 example 5-1: read-modify-write instructions on an i/o port ....................................................... 22 example 6-1: changing prescaler (timer0 wdt).......... 26 example 6-2: changing prescaler (wdt timer0).......... 26 list of figures figure 3-1: pic16c5x series block diagram .................... 8 figure 3-2: clock/instruction cycle .................................. 11 figure 4-1: pic16c54/cr54/c55 program memory map and stack....................................................... 13 figure 4-2: pic16c56 program memory map and stack....................................................... 13 figure 4-3: pic16c57 program memory map and stack....................................................... 13 figure 4-4: pic16c54/cr54/c56 register file map ....... 14 figure 4-5: pic16c55 register file map ......................... 14 figure 4-6: pic16c57 register file map ......................... 14 figure 4-7: status register (address:03h)................... 16 figure 4-8: option register........................................... 17 figure 4-9: loading of pc branch instructions - pic16c54/cr54/c55 .................................... 18 figure 4-10: loading of pc branch instructions - pic16c56 ...................................................... 18 figure 4-11: loading of pc branch instructions - pic16c57 ...................................................... 18 figure 4-12: direct/indirect addressing.............................. 20 figure 5-1: equivalent circuit for a single i/o pin............ 21 figure 5-2: successive i/o operation .............................. 22 figure 6-1: timer0 block diagram ................................... 23 figure 6-2: electrical structure of t0cki pin ................... 23 figure 6-3: timer0 timing: internal clock/no prescale ............................ 24 figure 6-4: timer0 timing: internal clock/prescale 1:2............................ 24 figure 6-5: timer0 timing with external clock ............... 25 figure 6-6: block diagram of the timer0/wdt prescaler 26 figure 7-1: configuration word for pic16c54/cr54/c55/c56/c57 ..................... 27 figure 7-2: crystal operation or ceramic resonator (hs, xt or lp osc configuration) ................ 28 figure 7-3: external clock input operation (hs, xt or lp osc configuration) ................ 28 figure 7-4: external parallel resonant crystal oscillator circuit............................................. 29 figure 7-5: external series resonant crystal oscillator circuit............................................. 29 figure 7-6: rc oscillator mode........................................ 30 figure 7-7: simplified block diagram of on-chip reset circuit.................................... 31 figure 7-8: electrical structure of mclr/v pp pin ........... 32 figure 7-9: external power-on reset circuit (for slow v dd power-up).............................. 32 figure 7-10: time-out sequence on power-up (mclr not tied to v dd ) ................................ 33 figure 7-11: time-out sequence on power-up (mclr tied to v dd ): fast v dd rise time..... 33
1995 microchip technology inc. ds30015m-page 127 pic16c5x figure 7-12: time-out sequence on power-up (mclr tied to v dd ): slow v dd rise time .... 33 figure 7-13: watchdog timer block diagram .................... 35 figure 7-14: brown-out protection circuit 1 ...................... 36 figure 7-15: brown-out protection circuit 2 ...................... 36 figure 8-1: general format for instructions ..................... 39 figure 9-1: picmaster system configuration............... 51 figure 10-1: load conditions - pic16c54/55/56/57 .......... 64 figure 10-2: external clock timing - pic16c54/55/56/57 . 65 figure 10-3: clkout and i/o timing - pic16c54/55/56/57 ....................................... 67 figure 10-4: reset, watchdog timer, and device reset timer timing - pic16c54/55/56/57 ............... 68 figure 10-5: timer0 clock timings - pic16c54/55/56/57 . 69 figure 11-1: typical rc oscillator frequency vs. temperature .................................................. 71 figure 11-2: typical rc oscillator frequency vs. v dd , c ext = 20 p f .......................................... 72 figure 11-3: typical rc oscillator frequency vs. v dd , c ext = 100 p f ....................................... 72 figure 11-4: typical rc oscillator frequency vs. v dd , c ext = 300 p f ....................................... 72 figure 11-5: typical i pd vs. v dd , watchdog disabled........................................ 73 figure 11-6: maximum i pd vs. v dd , watchdog disabled........................................ 73 figure 11-7: typical i pd vs. v dd , watchdog enabled......................................... 73 figure 11-8: maximum i pd vs. v dd , watchdog enabled......................................... 73 figure 11-9: v th (input threshold voltage) of i/o pins vs. v dd ................................................................ 74 figure 11-10:v ih , v il of mclr , t0cki and osc1 (in rc mode) vs. v dd .................................... 74 figure 11-11:v th (input threshold voltage) of osc1 input (in xt, hs, and lp modes) vs. v dd ............... 74 figure 11-12:typical i dd vs. frequency (external clock, 25 c) ................................... 75 figure 11-13:maximum i dd vs. frequency (external clock, ?0 c to +85 c) .................. 75 figure 11-14:maximum i dd vs. frequency (external clock ?5 c to +125 c) ................. 76 figure 11-15:wdt timer time-out period vs. v dd ............ 76 figure 11-16:transconductance (gm) of hs oscillator vs. v dd ................................................................ 76 figure 11-17:transconductance (gm) of lp oscillator vs. v dd ................................................................ 77 figure 11-18:i oh vs. v oh , v dd = 3 v .................................. 77 figure 11-19:transconductance (gm) of xt oscillator vs. v dd ................................................................ 77 figure 11-20:i oh vs. v oh , v dd = 5 v .................................. 77 figure 11-21:i ol vs. v ol , v dd = 3 v ................................... 78 figure 11-22:i ol vs. v ol , v dd = 5 v ................................... 78 figure 12-1: load conditions ............................................. 85 figure 12-2: external clock timing - pic16cr54.............. 86 figure 12-3: clkout and i/o timing - pic16cr54 ......... 88 figure 12-4: reset, watchdog timer, and device reset timer timing - pic16cr54............................ 89 figure 12-5: timer0 clock timings - pic16cr54.............. 90 figure 13-1: typical rc oscillator frequency vs. temperature .................................................. 91 figure 13-2: typical rc oscillator frequency vs. v dd , c ext = 20 p f ......................................... 92 figure 13-3: typical rc oscillator frequency vs. v dd , c ext = 100 p f ....................................... 92 figure 13-4: typical rc oscillator frequency vs. v dd , c ext = 300 p f....................................... 93 figure 13-5: typical i pd vs. v dd , watchdog enabled ........................................ 93 figure 13-6: maximum i pd vs. v dd , watchdog enabled ........................................ 93 figure 13-7: v th (input threshold voltage) of i/o pins vs. v dd ................................................................ 94 figure 13-8: v ih , v il of mclr , t0cki and osc1 (in rc mode) vs. v dd .................................... 94 figure 13-9: v th (input threshold voltage) of osc1 input (in xt, hs, and lp modes) vs. v dd .............. 94 figure 13-10:typical i dd vs. frequency (external clock 25 c) .................................... 95 figure 13-11:maximum i dd vs. frequency (external clock ?0 c to +85 c)................... 96 figure 13-12:wdt timer time-out period vs. v dd ............ 97 figure 13-13:transconductance (gm) of hs oscillator vs. v dd ................................................................ 97 figure 13-14:transconductance (gm) of lp oscillator vs. v dd ................................................................ 98 figure 13-15:transconductance (gm) of xt oscillator vs. v dd ................................................................ 98 figure 13-16:i oh vs. v oh , v dd = 3 v.................................. 98 figure 13-17:i oh vs. v oh , v dd = 5 v.................................. 98 figure 13-18:i ol vs. v ol , v dd = 3 v................................... 99 figure 13-19:i ol vs. v ol , v dd = 5 v................................... 99 list of tables table 1-1: pic16c5x family of devices ...........................4 table 3-1: pic16c54/cr54/c56 pinout description .........9 table 3-2: pic16c55/c57 pinout description ................ 10 table 4-1: special function register summary ............. 15 table 5-1: summary of port registers ........................... 21 table 6-1: registers associated with timer0 ................ 24 table 7-1: capacitor selection for ceramic resonators - pic16c54/55/56/57 ....................................... 28 table 7-2: capacitor selection for crystal oscillator - pic16c54/55/56/57 .. 28 table 7-3: capacitor selection for ceramic resonators - pic16cr54 ......... 29 table 7-4: capacitor selection for crystal oscillator - pic16cr54............... 29 table 7-5: reset conditions for special registers ......... 31 table 7-6: reset conditions for all registers................. 31 table 7-7: summary of registers associated with the watchdog timer ............................................ 35 table 7-8: to /pd status after reset ............................. 36 table 7-9: events affecting to /pd status bits .............. 36 table 8-1: opcode field descriptions ......................... 39 table 8-2: instruction set summary ............................... 40 table 9-1: picmaster probe specification.................. 52 table 9-2: development system packages.................... 55 table 10-1: cross reference of device specs for oscillator configurations (rc, xt & 10) and frequencies of operation (commercial devices) .............. 58 table 10-2: cross reference of device specs for oscillator configurations (hs, lp & jw) and frequencies of operation (commercial devices) .............. 58 table 10-3: external clock timing requirements - pic16c54/55/56/57 ....................................... 65 table 10-4: clkout and i/o timing requirements - pic16c54/55/56/57 ....................................... 67
pic16c5x ds30015m-page 128 1995 microchip technology inc. table 10-5: reset, watchdog timer, and device reset timer - pic16c54/55/56/57 ........................... 68 table 10-6: timer0 clock requirements - pic16c54/55/56/57 ....................................... 69 table 11-1: rc oscillator frequencies ............................. 71 table 11-2: input capacitance for pic16c54/56 .............. 78 table 11-3: input capacitance for pic16c55/57 .............. 78 table 12-1: cross reference of device specs for oscillator configurations and frequencies of operation (commercial devices).................................... 80 table 12-2: external clock timing requirements - pic16cr54 .................................................... 86 table 12-3: clkout and i/o timing requirements - pic16cr54 .................................................... 88 table 12-4: reset, watchdog timer, and device reset timer - pic16cr54 ....................................... 89 table 12-5: timer0 clock requirements - pic16cr54 .... 90 table 13-1: rc oscillator frequencies ............................. 91 table 13-2: input capacitance for pic16cr54................. 99 table d-1: pic16c5x family of devices....................... 117 table d-2: pic16c62x family of devices..................... 118 table d-3: pic16c6x family of devices....................... 119 table d-4: pic16c7x family of devices....................... 120 table d-5: pic16c8x family of devices....................... 121 table d-6: pic17cxx family of devices ...................... 122 table d-7: pin compatible devices ............................... 123
1995 microchip technology inc. ds30015m-page 129 pic16c5x connecting to microchip bbs connect worldwide to the microchip bbs using the compuserve ? communications network. in most cases a local call is your only expense. the microchip bbs connection does not use compuserve member ship services, therefore, you do not need compuserve membership to join microchip's bbs . there is no charge for connecting to the bbs, except toll charge to compuserve access number, where applicable. you do not need to be a compuserve member to take advantage of this connection (you never actually log in to compuserve). the procedure to connect will vary slightly from country to country. please check with your local compuserve agent for details if you have a problem. compuserve service allows multiple users at baud rates up to 14,400 bps. the following connect procedure applies in most locations: 1. set your modem to 8 bit, no parity, and one stop (8n1). this is not the normal compuserve setting which is 7e1. 2. dial your local compuserve access number. 3. depress and a garbage string will appear because compuserve is expecting a 7e1 setting. 4. type +, depress and host name: will appear. 5. type mchipbbs, depress < enter ? > and you will be connected to the microchip bbs. in the united states, to ?d compuserve's phone number closest to you, set your modem to 7e1 and dial (800) 848-4480 for 300-2400 baud or (800) 331-7166 for 9600-14400 baud connection. after the system responds with host name: type, network, depress < enter ? > and follow compuserve's directions. for voice information (or calling from overseas), you may call (614) 457-1550 for your local compuserve number. access to the internet microchips current www address is listed on the back page of this data sheet under worldwide sales & service - americas - corporate of?e. trademarks: picmaster and picstart are trademarks of microchip technology inc. pic is a registered trademark of microchip technology incorporated in the u.s.a. pro mate, fuzzy lab, the microchip logo and name are trademarks of microchip technology incorporated. fuzzy tech is a registered trademark of inform software corporation. i 2 c is a trademark of philips corporation. ibm, ibm pc-at are registered trademarks of international business machines corp. pentium is a trademark of intel corporation. ms-dos and microsoft windows are registered trademarks of microsoft corporation. windows is a trademark of microsoft corporation. compuserve is a registered trademark of compuserve incorporated. all other trademarks mentioned herein are the property of their respective companies. this document was created with framemake r404
pic16c5x ds30015m-page 130 1995 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip product. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (602) 786-7578. please list the following information, and use this outline to provide us with your comments about this data sheet. 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you ?d the organization of this data sheet easy to follow? if not, why? 4. what additions to the data sheet do you think would enhance the structure and subject? 5. what deletions from the data sheet could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document? 8. how would you improve our software, systems, and silicon products? to: technical publications manager re: reader response total pages sent from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n literature number: questions: fax: (______) _________ - _________ ds30015m pic16c5x device:
1995 microchip technology inc. ds30015m-page 131 pic16c5x pic16c54/55/56/57 product identification system to order or obtain information (e.g., on pricing or delivery) refer to the factory or the listed sales of?e. pic16cr54 product identification system to order or obtain information (e.g., on pricing or delivery) refer to the factory or the listed sales of?e. p ar t no . -xx x /xx xxx pattern package temperature range oscillator type device device pic16c54, pic16c54t (2) pic16c55, pic16c55t (2) pic16c56, pic16c56t (2) pic16c57, pic16c57t (2) oscillator type rc lp xt hs 10 b (1) = resistor capacitor = low power crystal = standard crystal/resonator = high speed crystal = 10 mhz crystal = no type for jw (3) devices temperature range b (1) i e =0 c to +70 c (commercial) = -40 c to +85 c (industrial) = -40 c to +125 c (automotive) package jw p s so sp ss = windowed cerdip = pdip = die in waf? pack = soic (gull wing, 300 mil body) = skinny pdip (28 pin, 300 mil body) = ssop (209 mil body) pattern 3-digit pattern code for qtp (blank otherwise) examples: a) pic16c54 - xt/pxxx = "xt" oscillator, commercial temp., pdip, qtp pattern. b) pic16c55 - xti/so = "xt" oscillator, industrial temp., soic (otp device) c) pic16c55 /jw = commercial temp. cerdip with window. d) pic16c57 - rc/s = "rc" oscillator, com- mercial temp., dice in waf? pack. note 1: b = blank 2: t = in tape and reel - soic, ssop packages only. 3: uv erasable devices are tested to all available voltage/frequency options. erased devices are oscillator type rc. the user can select rc, lp, xt or hs oscillators by programming the appro- priate con?uration bits. p ar t no . -xx x /xx xxx pattern package temperature range oscillator type device device pic16cr54, pic16cr54t (2) oscillator type rc lp xt hs 10 = resistor capacitor = low power crystal = standard crystal/resonator = high speed crystal = 10 mhz crystal temperature range b (1) i e =0 c to +70 c (commercial) = -40 c to +85 c (industrial) = -40 c to +125 c (automotive) package p s so ss = pdip = die in waf? pack = soic (gull wing, 300 mil body) = ssop (209 mil body) pattern 3-digit pattern code for rom (blank otherwise) examples: a) pic16cr54 - xt/p169 = "xt" oscillator, commercial temp., pdip with rom pattern 169. b) pic16cr54 - lp i/so592 = "lp" oscillator, industrial temp., soic device with rom code 592. note 1: b = blank 2: t = in tape and reel - soic, ssop packages only. sales and suppor t products supported by a preliminary data sheet may possibly have an errata sheet describing minor operational differences and recommended workarounds. to determine if an errata sheet exists for a particular device, please contact one of the following: your local microchip sales of?e (see below) the microchip corporate literature center u.s. fax: (602) 786-7277 the microchips bulletin board, via your local compuserve number (compuserve membership not required). please specify which device, revision of silicon and data sheet (include literature #) you are using. for latest version information and upgrade kits for microchip development tools, please call 1-800-755-2345 or 1-602-786-7302. 1. 2. 3. this document was created with framemake r404
1995 microchip technology inc. ds30015m-page 132 w orldwide s ales & s ervice asia/pacific hong kong microchip technology unit no. 3002-3004, tower 1 metroplaza 223 hing fong road kwai fong, n.t. hong kong tel: 852 2 401 1200 fax: 852 2 401 3431 korea microchip technology 168-1, youngbo bldg. 3 floor samsung-dong, kangnam-ku, seoul, korea tel: 82 2 554 7200 fax: 82 2 558 5934 singapore microchip technology 200 middle road #10-03 prime centre singapore 188980 tel: 65 334 8870 fax: 65 334 8850 taiwan microchip technology 10f-1c 207 tung hua north road taipei, taiwan, roc tel: 886 2 717 7175 fax: 886 2 545 0139 europe united kingdom arizona microchip technology ltd. unit 6, the courtyard meadow bank, furlong road bourne end, buckinghamshire sl8 5aj tel: 44 0 1628 851077 fax: 44 0 1628 850259 france arizona microchip technology sarl 2 rue du buisson aux fraises 91300 massy - france tel: 33 1 69 53 63 20 fax: 33 1 69 30 90 79 germany arizona microchip technology gmbh gustav-heinemann-ring 125 d-81739 muenchen, germany tel: 49 89 627 144 0 fax: 49 89 627 144 44 italy arizona microchip technology srl centro direzionale colleoni palazzo pegaso ingresso no. 2 via paracelso 23, 20041 agrate brianza (mi) italy tel: 39 039 689 9939 fax: 39 039 689 9883 japan microchip technology intl. inc. benex s-1 6f 3-18-20, shin yokohama kohoku-ku, yokohama kanagawa 222 japan tel: 81 45 471 6166 fax: 81 45 471 6122 12/04/95 americas corporate of?e microchip technology inc. 2355 west chandler blvd. chandler, az 85224-6199 tel: 602 786-7200 fax: 602 786-7277 technical support: 602 786-7627 web: http://www.mchip.com/microchip atlanta microchip technology inc. 500 sugar mill road, suite 200b atlanta, ga 30350 tel: 770 640-0034 fax: 770 640-0307 boston microchip technology inc. 5 mount royal avenue marlborough, ma 01752 tel: 508 480-9990 fax: 508 480-8575 chicago microchip technology inc. 333 pierce road, suite 180 itasca, il 60143 tel: 708 285-0071 fax: 708 285-0075 dallas microchip technology inc. 14651 dallas parkway, suite 816 dallas, tx 75240-8809 tel: 214 991-7177 fax: 214 991-8588 dayton microchip technology inc. suite 150 two prestige place miamisburg, oh 45342 tel: 513 291-1654 fax: 513 291-9175 los angeles microchip technology inc. 18201 von karman, suite 455 irvine, ca 92715 tel: 714 263-1888 fax: 714 263-1338 new york microchip technology inc. 150 motor parkway, suite 416 hauppauge, ny 11788 tel: 516 273-5305 fax: 516 273-5335 san jose microchip technology inc. 2107 north first street, suite 590 san jose, ca 95131 tel: 408 436-7950 fax: 408 436-7955 information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. no representation or warranty is given and no liability is assumed by microchip technology incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. use of microchips products as critical components in life support systems is not authorized except with express written approval by microchip. no licenses are conveyed, implicitly or otherwise, under any intellectual property rights. the microchip logo and name are registered trademarks of microchip technology inc. all rights reserved. all other trademarks mentioned herein are the property of their respective companies. all rights reserved. 1995, microchip technology incorporated, usa.

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